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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture…

• 5 min read
AF , uvm , Specman , debug , Functional Verification , Incisive , UVM ML , e language , simulation

Verification

Generic dynamic run-time operations with e reflection Part II

Field access and method invocations In the previous blog , we explained what are…

• 4 min read
AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Analog/Custom Design

It’s Late, But the Party is Just Getting Started

Key Findings: Many more chip programs are crossing the tipping point and need advanced…

• 6 min read
AMS , analog behavior , AMS-Designer , AMS Designer , analog behavioral models , analog/mixed-signal , AMS Verification

SoC and IP

Call for Papers Now Open – CDNLive Silicon Valley

CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides…

• less than a min read
IP , EDA conference , CDNLive , IP papers , EDA papers

Whiteboard Wednesdays

Whiteboard Wednesdays—PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence…

• less than a min read
performance , Whiteboard Wednesdays , PCIe , latency , PCI Express

System, PCB, & Package Design 

What's Good About Using Sigrity and Cadence SiP Digital to Reduce Design Costs? Check…

This week, you can view a couple of videos where customers describe how they used…

• 1 min read
SiP , Digital SiP design , Power Integrity , Layout , Signal Integrity , PCB design , Sigrity

Whiteboard Wednesdays

Whiteboard Wednesdays—Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable…

• less than a min read
Whiteboard Wednesdays , IP , Mac , 10/40G , Ethernet , SerDes , PCS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Artwork Film Capabilities? 16.6 Has Several…

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , artwork , SPB , PCB Editor , Layout , design , PCB design , Allegro PCB Editor , Allegro

Digital Design

Five-Minute Tutorial: One More Look at EM Models

Just when you thought you were done setting up EM model files, along came another…

• 2 min read
Voltus , Digital Implementation , Power Analysis , EM , five minute tutorial

Whiteboard Wednesdays

Whiteboard Wednesdays—DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training…

• less than a min read
Whiteboard Wednesdays , training , DDR , timing

System, PCB, & Package Design 

What's Good About Allegro PCB Editor New Slide Capabilities? 16.6 has Several New…

The 16.6 Allegro PCB Editor release's new ‘Slide’ command utilizes a move-intersect…

• 8 min read
PCB , PCB Layout and routing , interconnects , Allegro GUI , Allegro 16.6 , cadence , Routing , DRC , Placement Edit , diff pair , SPB , PCB Editor , High-Density Interconnect , Layout , Allegro router , PCB design , Spacing , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps…

• less than a min read
Whiteboard Wednesdays , IP , NAND flash

Verification

Looking Back at a Great Week for System Design!

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had…

• 3 min read
debug , System Design and Verification , embedded software , hybrid , ARM TechCon 2014 , ARM , verification

Verification

Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

In its 10th year now, ARM TechCon is in full swing this week at the Santa Clara Convention…

• 3 min read
NVIDIA , Palladium , hybrid , Emulation , ARM Fast Models , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Ethernet in Cars

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing…

• less than a min read
communication protocol , Automotive Ethernet , Ethernet , open standard , interoperability

Verification

Troubleshooting Incisive Errors/Warnings with nchelp/ncbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
nchelp , Incisive , error , xcelium simulator , troubleshooting , mnemonic , xcelium , utilities , xmhelp

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Move Lines/Text to Different Classes? Check…

Beginning with the 16.6 Allegro PCB Editor release, lines and text can now be moved…

• 1 min read
PCB , Allegro 16.6 , SPB , PCB Editor , Layout , Grzenia , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Select the Right Performance for a 802.11ac/Advanced LTE A…

In this week's Whiteboard Wednesdays video, Priyank Shukla removes the mystery behind…

• less than a min read
wireless , Whiteboard Wednesdays , 802.11x , wireless AFE , analog front end , AFE , LTE

Digital Design

New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation…

One question we often hear from experienced physical design engineers migrating to…

• 2 min read
P&R , encounter digital implementation system , place and route , Rapid Adoption Kits , RAKs , physical implementation
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