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Breakfast Bytes

EDPS Cyber Security Workshop: "Don't Let Convenience Trump Security"

EDPS, the Electronic Design Process Symposium, always has the second of the two days…

Paul McLellan 28 Apr 2016 • 4 min read

security , Monterey , chris eagle , EDPS , cyber security , naval postgraduate school , Breakfast Bytes

Breakfast Bytes

FD-SOI: Can I Design It and Manufacture It?

Yesterday I covered the analysis by ARM and VLSI Research on FD-SOI from the symposium…

Paul McLellan 27 Apr 2016 • 4 min read

28 FD-SOI , Samsung , VSLI Research , GlobalFoundries , ARM , FD-SOI

SoC and IP

CDNLive Silicon Valley 2016—The Bigger IP Picture

When a presentation makes us think about an industry on a whole new level and rethink…

Steve Brown 26 Apr 2016 • 1 min read

CDNLive , ip cores , Design IP and Verification IP

Whiteboard Wednesdays

Whiteboard Wednesdays - Floating-Point Core of Tensilica Vision P5 DSP

In this week's Whiteboard Wednesdays video, Dennis Crespo explains the optional vector…

References4U 26 Apr 2016 • less than a min read

Whiteboard Wednesdays , IP , Computer Vision , Tensilica , imaging , floating point , Tensilica Vision P5 DSP

Analog/Custom Design

Virtuoso Video Diary: Flexible Connectivity Support of Dummy Devices

Virtuoso Video Diary is envisaged to be an online journal that will relay information…

Rishu Misri Jaggi 26 Apr 2016 • 3 min read

dummy backannotation , Physical placement and layout , backannotation , Layout , Virtuoso , dummy abutment , dummy instances , dummy instance backannotation , dummy devices , dummy instance abutment , Virtuoso Layout Suite , dummies , VLS XL , custom design technology , Virtuoso Layout Suite XL , Abutment

Breakfast Bytes

FD-SOI: Is It Really a Thing?

Apparently, asking if something is really a thing is really a thing. So, recently…

Paul McLellan 26 Apr 2016 • 8 min read

FinFET , GlobalFoundries , ARM , FD-SOI

System, PCB, & Package Design

What's Good About the Latest Constraint Manager? The 16.6-2015 Release has Several…

Significant enhancements to the 16.6-2015 Constraint Manager release have been made…

Jerry GenPart 25 Apr 2016 • 3 min read

PCB , SI , Allegro 16.6 , SigXP UI , Constraint Manager , Signal Integrity , Constraints , Grzenia

Analog/Custom Design

The Leader of the Orchestra: Getting Started with Virtuoso ADE Verifier

The members of an orchestra are often great virtuosi on their own instruments, but…

TeamADE 25 Apr 2016 • 3 min read

verifier , Virtuoso ADE Verifier , Virtuoso Analog Design Environment , Analog Design Environment

Breakfast Bytes

Patents and Standards, Managing the Challenge

One challenge with standards is the desire to avoid unknowingly incorporating patents…

Paul McLellan 25 Apr 2016 • 5 min read

vlsi technology , Rambus , ieee patent policy , GSM , loa , patent , IEEE-SA , IEEE , letter of assurance , Breakfast Bytes , standard

Breakfast Bytes

Andrew Kahng on PPAC Scaling Below 7nm

Last week Dr. Andrew Kahng came to town. He was at CDNLive, where his presentation…

Paul McLellan 22 Apr 2016 • 5 min read

ucsd , roadmap , ITRS , Cadence Academic Network , kahng , andrew kahng , 5nm , 7nm , power

Academic Network

Academic Track Makes Its Debut at CDNLive Silicon Valley

For the first time at CDNLive Silicon Valley, Cadence Academic Network hosted an…

susarla 21 Apr 2016 • 2 min read

Cadence Academic Network , CDNLive , academia

Breakfast Bytes

Phil Moorby and the History of Verilog

Last Saturday there was a gala event at the Computer History Museum in Mountain View…

Paul McLellan 21 Apr 2016 • 6 min read

verilog-xl , gateway design automation , SystemVerilog , Gateway , Phil Moorby , Verilog , computer history museum , chm

SoC and IP

50 Years of Turning Optical Dreams into Reality

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues…

Steve Brown 20 Apr 2016 • 3 min read

Optical , PCIe Gen4 , OFC , Fiber , PCIe

Breakfast Bytes

Ann Winblad Masterclass

Normally the Stanford VLAB meets in Menlo Park, but occasionally they make a foray…

Paul McLellan 20 Apr 2016 • 5 min read

ann winblad , vlab , hummer winblad , venture capital

Whiteboard Wednesdays

Whiteboard Wednesdays - The Future of Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen looks at the future of neural…

References4U 19 Apr 2016 • less than a min read

Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , neural networks

Breakfast Bytes

Open Server Summit: How to Install 5,000 Servers Per Day

There are only a few end markets for semiconductors that really drive the technology…

Paul McLellan 19 Apr 2016 • 6 min read

Open Server Summit , servers , datacenter

Verification

Building Efficient Scoreboards

A “scoreboard” is a verification component that checks the data sent to the DUT against…

teamspecman 18 Apr 2016 • 7 min read

Breakfast Bytes

"Interoperability is the Only Way to Prove Standards Compliance"

At the recent TSMC Technology Symposium, Cadence and Mellanox demonstrated multi…

Paul McLellan 18 Apr 2016 • 3 min read

pcie 4.0 , data center , PHY , mellanox , PCIe , mobile , PCI Express

Breakfast Bytes

Memory in China: XMC

Yesterday I covered the first half of the CASPA meeting last Saturday about memory…

Paul McLellan 15 Apr 2016 • 4 min read

China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

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