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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

Modus Test Solution—Tests Great, Less Filling

Today Cadence announced the latest product in the "us" series of next-generation…

• 4 min read
modus test , low pincount test , modus , Test , codec , 2D elastic compression , test compression , Breakfast Bytes

System, PCB, & Package Design 

Cadence Online Support – Empowering Learning! New Learnings from December 2015

Documentation plays a significant role in helping to understand the software. Cadence…

• 5 min read
Cadence Online Support , IC package design , Cadence Help , Cadence Application Notes , RAKs , Allegro

Academic Network

How to Start as an IT Intern and Become a Cadence Employee

Here at Cadence we are very proud to provide internships to students and graduates…

• 2 min read
Interns , Cadence Academic Network

SoC and IP

DesignCon Demonstration of IP for PCIe 4.0 and 16Gbps Multi-Protocol PHY

We enjoyed sharing our latest news with the many people who visited our booth at…

• less than a min read
DesignCon , PCIe Gen4 , pcie4 , Design IP and Verification IP , SerDes

Breakfast Bytes

Conway's Law and the Changing Structure of Automobile Companies

There is a law in business organization known as Conway's Law. This states that:…

• 4 min read
Apple , organizational structure , google , tesla , automobile companies , conway's law

Breakfast Bytes

Moore's Law from 50,000 Feet

Moore's Law is in the news again since Intel, having maintained for years that nothing…

• 5 min read
semiconductor economics , ray kurzweil , moore's law , kurzweil , NASA , Breakfast Bytes

Academic Network

Education Weeks in Abu Dhabi

Abu Dhabi, the capitol of United Arab Emirates (UAE), has a vibrant academic scene…

• 2 min read
Cadence Academic Network , Abu Dhabi University , Virtuoso , microelectronics , university program

Breakfast Bytes

DesignCon: the 16Gbps Show

I always find DesignCon a slightly weird conference to attend. I swim in the semiconductor…

• 5 min read
DesignCon , 16gbps , PCIe 4 , designcon16 , measurement , Signal Integrity , SerDes , Sigrity

Whiteboard Wednesdays

Whiteboard Wednesdays—Key Metrics for Embedded Neural Networks

In this week's Whiteboard Wednesdays video, Chris Rowen takes a closer look at the…

• less than a min read
Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , embedded neural networks

System, PCB, & Package Design 

What's Good About the Altium to Allegro PCB Editor Translator? It’s Now Available…

The current 16.6 HotFix now provides support for the Altium to Allegro PCB Editor…

• 2 min read
PCB , Allegro 16.6 , DEHDL , SPB , Design Entry HDL , PCB design , Grzenia , Allegro PCB Editor , Allegro

Breakfast Bytes

Misfit Shine 2 Lasts for 6 Months on a Coin Cell. How Do They Do That?

You can't go for very long without hearing about the Internet of Things (IoT) in…

• 3 min read
ClariTek , IoT , Misfit , Shine 2 , Breakfast Bytes , Patrick Mannion

Breakfast Bytes

IEDM Examines Options for 5nm...Academics and Industry Examine the Options

At IEDM in December, there was a full-day course looking at the options for transistors…

• 3 min read
transistors , interconnect , feol , carbon nanotube , optical interconnect , FinFET , beol , IEDM , Breakfast Bytes , devices

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Differential Pair Return Path Vias? Significant…

The Allegro PCB Editor 16.6-2015 release (requires login) now provides support for…

• 7 min read
PCB Layout and routing , diff pairs , Allegro 16.6 , SPB , differential pair , PCB design and layout , Grzenia , Allegro PCB Editor , differential pairs , return path vias

Academic Network

Genus Synthesis Solution 15.2 Now Available to Academia

To support academia using the latest industry-standard tools, Cadence's Genus Synthesis…

• 1 min read
Genus , Cadence Academic Network , academia

Verification

Using Tables to Handle Configurability in Incisive Enterprise Specman

Most, if not all, designs which are being verified today are configurable. This is…

• 2 min read
IntelliGen , configurable designs , Specman , tech tips , Funcional Verification , Incisive Enterprise Specman

Breakfast Bytes

Designing USB 3.1? You Need Sigrity 2016

The most important new connector in town (especially if that town was Las Vegas during…

• 4 min read
USB 3.0 , USB Power Delivery , USB Type-C , usb 3.1 gen 1 , usb 3.1 gen 2 , sigrity 2016 , USB , ibis-ami model , Sigrity , USB 3.1 , ces2016 , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—SSD Controllers with Tensilica Processors

In this week's Whiteboard Wednesdays video, Neil Robinson follows up on last week…

• less than a min read
Whiteboard Wednesdays , IP , Neil Robinson , Tensilica , SSD controllers

Breakfast Bytes

Embedded Neural Network Summit—How to Build a Silicon Brain

On February 9, Cadence is hosting an all-day Embedded Neural Network Summit., with…

• 2 min read
deep learning , enns , Tensilica , convolutional neural networks , embedded neural networks , Breakfast Bytes

SoC and IP

New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivit…

PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface…

• 1 min read
PCIe Gen4 , pcie4 , 16Gbps PHY IP , SerDes , SerDes IP
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