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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuoso IC 5.1.41 Was Good but Virtuoso IC 6.1 is Better

With the recent release of unified custom/analog flow that is based on the latest…

• 3 min read
Analog Design Environment , Virtuoso IC6.1.5 , IC 6.1 , analog , Constraint-driven , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Custom IC Design , SKILL++ , SKILL

Verification

NEW Enterprise Planner Videos!

Videos on Enterprise Planner: What's it worth to you? Submitted By MDV…

• 1 min read
videos , Verification methodology , Functional Verification , Metric Driven Verification , vPlan , verification planning , Enterprise Manager , Enterprise Planner , Plan and metrics management , MDV

Digital Design

Encounter Quick Tip: How to Repair Command Line Navigation When Launching via bs…

When two users report the same issue in the same week I'm glad I can share the problem…

• 1 min read
EDI , encounter , Digital Implementation , Encounter Digital Implementation , command line , bsub

SoC and IP

New Memory Technologies, New Possibilities

As a complete gadget geek, it’s always exciting to play with the latest technological…

• 1 min read
controller IP , Design IP , IP , Memory , DDR4 , wide i/o , SoC , storage , Denali , DDR , SoC Realization , Wide-IO

Verification

Combating System-Level Design Confusion

I would like to add my thanks to Gary Smith for his short "Industry Note" titled…

• 5 min read
silicon virtual prototype , virtual platforms , software virtual prototype , TLM , virtual prototypes , architectural , embedded software , Gary Smith , System-Level Design , architects workbench , SystemC , C++ , ESL , System Design and Verification

Verification

1st Anniversary of the Team Verify Blog!

Verifiers rejoice: today is the 1st anniversary of the launch of this blog!!! To…

• 3 min read
workshops , NextOp , Low Power , ABV , methodology , Zocalo , metric driven verification (MDV) , Functional Verification , Formal Analysis , vPlan , ABVIP , formal , Coverage-Driven Verification , SoC , Kit , Chris Komar , Oski Technology , assertion synthesis , metric-driven verification , Twitter , assertions , SoC Connectivity , MDV , IEV , simulation , Formal verification , IFV , blog , Assertion-based verification

Verification

Video: Update on AMIQ’s DVT IDE and UVM 1.0 at DVCon 2011

The UVM 1.0 release was the big story of DVCon 2011, as it's the first verification…

• 1 min read
uvm , methodology , Functional Verification , Amitroaie , OVM , OVM e , e , DVT , ecosystem , DVcon , AMIQ , eRM , IDE , IES-XL

Verification

Why Can’t You Write My Assertions for Me? - Part 1

As regular readers know from previous posts , I have a lot of background in assertion…

• 3 min read
conformal , NextOp , ABV , Functional Verification , formal , CPF , CDC , Palladium , Incisive , assertion synthesis , assertions , Constraints , IEV , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About ADW’s Configuration Manager? Check out the ADW16.3 Release and

The ADW16.3 Allegro Design Workbench has a new Configuration Manager that simplifies…

• 1 min read
PCB , SPB16.3 , Allegro 16.3 , SPB 16.3 , Allegro Design Workbench , Library flow , Library and design data management , PCB Editor , design data management , design , Design Entry , ADW 16.3 , Librarians , library , PCB Capture , Schematic

Verification

Video: Formal Verification Service Provider Oski Technology at DVCon 2011

While there was a lot (justifiable) buzz around the UVM 1.0 release, formal and assertion…

• 1 min read
ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , formal , Oski Technology , DVcon , IEV , Formal verification , IFV , verification

System, PCB, & Package Design 

What's Good About PCB PI Discontinuity Modeling? See For Yourself in SPB16.3!

The current Allegro PCB Power Integrity (PI) tool is fast, but not accurate enough…

• 1 min read
PCB SI , PCB , SI , PI , SPB16.3 , Integrity Check , discontinuity modeling , PCB PI , Signal Intregrity , SigXP UI , SPB 16.3 , Power Integrity , High Speed , PCB power integrity , SPB , electromagnetic , PCB Signal integrity , Allegro PCB Editor , SI analysis and modeling , Allegro

RF Engineering

My Favorite nport Settings for Spectre and SpectreRF

The nport component located in analogLib can be used in circuits for Spectre and…

• 4 min read
nport , RF , RF Simulation , Circuit simulation , RFIC , Spectre RF , Analog Simulation , nport settings , Spectre , analogLib

System, PCB, & Package Design 

What's Good About Allegro PCB Editor 3D Viewing? Oh My – Check Out SPB16.3!

The SPB16.3 Allegro PCB Editor has a new 3D Viewer! Viewing a 3D rendering of the…

• less than a min read
PCB , PCB Layout and routing , SPB16.3 , mechanical parts , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , design , "PCB design" , PCB design , Allegro PCB Editor , 3D viewer , Allegro

Verification

Video: DVCon 2011 Update From NextOp CEO Yunshan Zhu

At DVCon 2011 I had the opportunity to catch-up with NextOp's CEO Yunshan Zhu, where…

• less than a min read
Cadence Connections , NextOp , uvm , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Zhu , Palladium XP , SVA , DVcon , assertion synthesis , MDV , IEV , Formal verification , IFV , IES-XL

Verification

Save The Date: Free Webinar on Automated SoC Connectivity Verification This Thursday…

We interrupt our technically oriented blogging to shamelessly promote a free webinar…

• 1 min read
ABV , methodology , Functional Verification , formal , SoC Connectivity , IEV , Formal verification , IFV

Analog/Custom Design

Is China Ready for Next Generation Mixed-signal Design?

A Chinese design engineer told me that his manager once told him: "You do not have…

• 4 min read
China , mixed-signal ToT , tech on tour , abstraction , EDA360 , analog , Mixed-Signal , Convergence , intent , japan , Silicon Realization , mixed signal , SoCs

Analog/Custom Design

Rapid Analog Prototyping - Handcrafted Layout Gets a Needed Productivity Boost

As more and more custom/analog designs migrate to advanced process nodes (<65nm)…

• 4 min read
AMS , parasitic-aware design , PAD , RAP , Virtuoso IC6.1.5 , custom/analog , PCells , Advanced Node , analog , Constraint-driven , IC 6.1.5 , Mixed-Signal , Virtuoso , rapid analog prototyping , Custom IC Design , modgens , Virtuoso Layout Suite , parasitics

Analog/Custom Design

Early Analysis is Key – Parasitic-Aware Design

Decreasing geometries and increasing design complexity are making the task of designing…

• 3 min read
parasitic-aware design , Analog Design Environment , PAD , Virtuoso IC6.1.5 , IC 6.1.5 , ADE , Virtuoso , ADE-GXL , ADE-XL , parasitics

System, PCB, & Package Design 

What's Good About Capture OLE Object Placing? You Can Easily Do This in SPB16.3!

Object Linking and Embedding ( OLE ) support in SPB16.3 Allegro Design Entry CIS…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Design Entry CIS , OrCAD Capture , SPB 16.3 , Capture CIS , Capture-CIS , OLE , SPB , design , OrCAD , object placing , Design Entry , PCB Capture
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