Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

C-to-Silicon Does Not Require a Library Characterization

One of the key strengths of C-to-Silicon Compiler (CtoS) over other ESL Synthesis…

• less than a min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , ESC , C-to-Silicon , ESL handoff , C-to-Silicon Compiler , ESL , architect

Verification

Blogger of the Quarter Award -- Thanks!!!

Little did I know that when I accepted an innocent looking meeting propsal from my…

• 1 min read
funtional verification , Specman , e

Verification

New Blog series- Team ESL

Cadence is well known for its leadership in system verification leveraging its HW…

• 1 min read
High-Level Synthesis , high-level synthesis adoption , System Design and Verification , embedded software , C-to-Silicon , ESL handoff , embedded SW engineer , Incisive Software Extensions , C-to-Silicon Compiler , ISX , Hardware/software co-verification , ESL

Verification

Exploring the Virtual Platform Part 4

Welcome to Part 4 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read
microsoft , System Design and Verification , QEMU virtual platform , vista , ARM , wind river , monta

Verification

Post-Show Thoughts on DesignCon 2009

Joe Hupcey posted some photos from the DesignCon show in Santa Clara last week, and…

• 1 min read
DesignCon , NXP , Functional Verification , coreuse , DVcon

Verification

Road Trip!

As at most companies these days, Cadence is doing what it can to minimize travel…

• 1 min read
Specman , Functional Verification , e , DVcon

System, PCB, & Package Design 

Focus Area: EDA Librarians - Manual Versus Automatic

Nope - I'm not talking about automobile transmissions ... I'll continue my series…

• 2 min read
SPB 16.2 , Library and design data management , APutomatic , PCB design , Librarians

Verification

Tech Pubs Tips Series Kickoff: Search for Single Character Words

[Team Specman welcomes the Technical Publications Team to our blog] Effectively documenting…

• 1 min read
Specman , C , e , Enterprise Manager , Incisive Enterprise Simulator (IES) , IES

Analog/Custom Design

Your Virtuoso MMSIM Portfolio 2009 Performance Outlook

John Pierce, Product Marketing Director for Virtuoso Simulation application gives…

• 1 min read
mixed-signal simulators , Chip-level simulation , MMSIM , Virtuoso IC 6.1.3 , Block-level simulation , RF design , AMS simulation , Circuit Design , Simulators , Custom IC Design , custom design technology

Digital Design

Constraint Construction: What's Its Function? Part 1 of 4

Have you found yourself frustrated at the lack of some decent timing constraints…

• 3 min read
Constraint Design , SoC-Encounter , Digital Implementation forums , SoC-Encounter 8.1 , 8.1 , Digital Implementation , Encounter Digital Implementation , Encounter Timing System , "SoC-Encounter"

SoC and IP

Memory's Recession: Actions and Realities

Now is the Winter of our Discontent: Five months into a memory industry recession…

• 7 min read

Digital Design

Programmatically Troubleshooting Timing Violations With "report_timing -collection…

Has something like the following ever happened to you? You've placed and optimized…

• 4 min read
Static timing analysis , CTE-TCL , Digital Implementation , scripting , tcl

Digital Design

How to Create a Repeating Power Switch Pattern with addPowerSwitch

I mentioned in my last post that I'd been having lots of fun with power switches…

• 2 min read
Low Power , Digital Implementation , addpowerswitch

Verification

Tech Tip - Double Wall Clock Performance with One Easy Step

[Please welcome guest blogger Silas McDermott, an Application Engineer in our Field…

• 2 min read
Specman , e , Aspect Oriented Programming , Incisive Enterprise Simulator (IES) , IES , AOP

Verification

Scalable OVM Register and Memory Package

Drawing on nearly a decade of experience, Cadence has just posted the first release…

• 2 min read
SystemVerilog , OVM , vr_ad , Register Package , e , eRM

Verification

Of EDA Vendors and Conferences

There's an interesting thread on Cool Verification ( http://www.coolverification…

• 1 min read
Functional Verification

System, PCB, & Package Design 

Brad Griffin Speaks at DesignCon - Give Him a Listen!!

If you were not lucky enough to be atDesignCon this week, and many of us were not…

• less than a min read
PDN , cadence , Digital SiP design , Advanced Node , IC Packaging & SiP design , SerDes , IC design , IC Package Physical layout and co-design , design chain

System, PCB, & Package Design 

What's Good About ASA Differential Pair Swapping? - The Secret's in the SPB16.2 Release

And the new features list just keeps going on and on - it's terrific! In the SPB16…

• 1 min read
SPB 16.2 , ASA , PCB design , differential Pair Swapping , Allegro

Verification

Exploring the Virtual Platform Part 3

Welcome to part 3 of the "Exploring the Virtual Platform" series. For readers just…

• 4 min read
CDNS - Fix Layout Hompage