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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

SoC and IP

New Blog: EDA360 Insider, for anyone involved with any aspect of system design

I’ve just started a new blog called the EDA360 Insider ( http://eda360insider.wordpress…

• less than a min read

SoC and IP

Samsung rolls 8Gbyte DDR3 SODIMM, Dell picks it up immediately, stuffs four into…

Samsung has announced that it is now shipping 8Gbyte DDR3 SODIMM SDRAM modules for…

• less than a min read

Verification

Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With…

Lately the tone of the trade press and blogs about the Silicon Valley electronics…

• less than a min read
uvm , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Chu , verification

Analog/Custom Design

Now Playing: Custom IC Videos-to-Go

I wanted to take a brief detour from my usual postings to point out a couple of new…

• 3 min read
IC 6.1 , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

DRAMeXchange ranks NAND Flash vendors for Q210. Samsung wins, again.

Last month, DRAMeXchange published rankings for the top “branded” NAND Flash vendors…

• 1 min read

Digital Design

Encounter Puzzler #2 Solution: Finding Registers Beneath a Hierarchy

Thanks to everyone who participated in this week's Encounter Puzzer . If you didn…

• 6 min read
dbGet , encounter , Digital Implementation , puzzler , tcl

SoC and IP

JEDEC launches new SSD reliability standards, plans in-depth SSD tutorial in San…

An article in ComputerWorld reports that JEDEC (www.jedec.org) has just announced…

• less than a min read

SoC and IP

Crucial SSDs hit $1/Gbyte, with a crucial caveat

The Bright Side of News (BSN, www.bsn.com) Web site reports today that Crucial is…

• less than a min read

Digital Design

Five-Minute Tutorial: Creating a NONDEFAULT Rule

Ah, the NONDEFAULT rule. This is a routing rule that is, well, not the default! It…

• 2 min read
nondefault rule , EDI system , tutorial , encounter , Digital Implementation , nondefault , five minute , five-minute

SoC and IP

Top 10 SSD benefits: Samsung publishes list

Samsung, SSD vendor and the world’s leader in Flash memory, has just published a…

• 1 min read

SoC and IP

Oracle optimizes Unbreakable Linux for SSDs. Improves access times by 137%.

This week at its OpenWorld event held in San Francisco, Oracle announced the Unbreakable…

• 1 min read

System, PCB, & Package Design 

What's Good About Differential Impedance in Allegro Constraint Manager? It's in SPB16

The ability to constrain or report Differential Impedance from within Constraint…

• 2 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , DRC , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , design , PCB design , Allegro PCB Editor , SI analysis and modeling , Differential Pair Support , power

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL -- Where Did My Data Go?

Last week I got to attend a "Social Media Summit" here at Cadence. Jeepers, a "summit…

• 3 min read
Analog Simulation , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

Samsung whacks DDR3 SDRAM with 36nm stick, knocks 30% off the cost. Elpida and Micron…

Samsung just announced that it is readying 4Q volume production of 2Gbit DDR3 chips…

• less than a min read

SoC and IP

STEC’s ZeusRAM DRAM-based 3.5-inch SSD has 23 microsecond latency, uses Flash for…

This week at Oracle OpenWorld, STEC introduced a DRAM-based, Flash-backed, 6Gbps…

• less than a min read

SoC and IP

Mars Reconnaissance Orbiter crashes, reboots for fifth time

On September 15, the Mars Reconnaissance Orbiter (MRO) went into “safe mode” for…

• 2 min read

Verification

e Templates and Aspect Oriented Programming

In a recent blog - " e Templates: A Nifty Way To Create Reusable Code ", Corey Goss…

• 2 min read
Specman , EDA , e , team specman , Aspect Oriented Programming , AOP , IES-XL

SoC and IP

Just how close to the end of NAND Flash are we?

One of the surprises that came from the many excellent presentations given at GlobalFoundrries…

• 1 min read

SoC and IP

PhotoFast SSD leverages PCIe x8 to smash past Gbyte/sec SSD transfer-rate barrie…

Want a really fast SSD? You’ll need really fast I/O and PhotoFast’s GM-PowerDrive…

• less than a min read
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