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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
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Breakfast Bytes

Memory in China: XMC

Yesterday I covered the first half of the CASPA meeting last Saturday about memory…

• 4 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Verification

RTL Signoff vs. Functional Signoff

The notion of signoff has many layers to it, both in terms of complexity but also…

• 4 min read
funtional verification , IMC , metric driven verification (MDV) , functional coverage , MDV , vManager

Breakfast Bytes

Memory, the Turning Point of Chinese Semiconductor Industry

I can't keep away from work. Saturday found me in the Cadence auditorium for the…

• 5 min read
China , Memory , xmc , NAND flash , 3d nand flash , DRAM , caspa , goldman sachs , ibs

Breakfast Bytes

TI and UI: Texas Instruments' Experience with the Common User Interface

Cadence's tools Genus, Innovus, and Tempus have a lot of functionality in common…

• 3 min read
Genus , Tempus , Joules , Voltus , Innovus , Bob Sussman , Texas Instruments , TI , Breakfast Bytes , common UI

Whiteboard Wednesdays

Whiteboard Wednesdays - Common Infrastructure Between Simulation VIP and Accelerated…

In this week's Whiteboard Wednesdays video, Arindam Guha discusses the common infrastructure…

• less than a min read
accelerated VIP , Verification IP , simulation VIP , simulation

Academic Network

Cadence Participates in 14 Spring Career Fairs

Rain or snow does not stop our Cadence employees from being the perfect brand ambassadors…

• 1 min read
university , Cadence Academic Network , campus recruitment , academia

System, PCB, & Package Design 

What's Good About the latest RF PCB? New capabilities in 16.6-2015!

The 16.6-2015 RF PCB release contains many new features and updates. Read on for…

• 4 min read
RF , Cadence Design Systems , 16.6 , SPB , Grzenia , Allegro

Breakfast Bytes

Qualcomm Looks to the Future: Steve Mollenkopf's CDNLive Keynote

Steve Mollenkopf, the CEO of Qualcomm Incorporated, gave one of the keynotes at CDNLive…

• 4 min read
mollenkopf , CDNLive , IoT , Qualcomm , Internet of Things , drone , mobile , Snapdragon , CDNLive Silicon Valley , ARM , datacenter , Breakfast Bytes

Verification

Modelling a Value Holder Template with the Value “new-ed” by Default

In many companies, there is a well-defined flow for handling monitored data items…

• 2 min read
IEEE 1647 , Specman , tech tips , e , e language , specman elite , Aspect Oriented Programming , AOP , verification

Breakfast Bytes

Jim Hogan and the Early Days of Virtuoso

I had lunch with Jim last week to get a little color on the early days of the Virtuoso…

• 3 min read
Hogan , james spoto , national , Virtuoso , daisy systems , chipmaster , Jim Hogan , SDA , SKILL

Academic Network

Announcement of MEMS Design Contest at DATE

On March 17 th in the Exhibition Theatre at DATE, there was the first public announcement…

• 3 min read
Cadence Academic Network , academia , MEMS Design Contest

Breakfast Bytes

AdaptIP Talk About Their High-Level Synthesis Approach at CDNLive

At this year's CDNLive, AdaptIP presented their experiences with high-level synthesis…

• 4 min read
802.11ah , CDNLive , adaptip , Stratus , viterbi decoder , high level synthesis , CDNLive Silicon Valley , FFT , HLS , Breakfast Bytes

Analog/Custom Design

Virtuosity: Things I Learned in January, February, and March 2016 by Browsing Cadence…

At CDNLive Silicon Valley this month, Cadence announced a new family of ADE tools…

• 6 min read
verifier , Explorer , Advanced Node , ADE , modgens , Assembler , VLS XL

Academic Network

What Are Rapid Adoption Kits, And Why Are They Great for Academia?

Academic research often requires the learning of new concepts and techniques in a…

• 1 min read
Cadence Academic Network

Breakfast Bytes

Tom Beckley's CDNLive Keynote: Addressing Complexity and Safety Challenges

Tom Beckley gave the final keynote before lunch here at CDNLive in Silicon Valley…

• 3 min read
Virtuoso Variation Option , Virtuoso ADE Verifier , Tom Beckley , CDNLive , CDNLive Silicon Valley 2016 , Virtuoso , CDNLive Silicon Valley , Virtuoso ADE Explorer , Virtuoso ADE Assembler , Breakfast Bytes

Breakfast Bytes

Mobile Unleashed...and Reviewed

I finished reading Don Dingee and Dan Nenni's book, Mobile Unleashed, the Origin…

• 5 min read
Apple , Simon Segars , Samsung , Qualcomm , mobile , ARM processors , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Relationships Between USB Specs

In this week's Whiteboard Wednesdays video, Jacek Duda describes the relationships…

• less than a min read
USB Power Delivery , Whiteboard Wednesdays , IP , USB Type-C , Jacek Duda , USB , USB-C , USB 3.1

Analog/Custom Design

Analog Design Resonance: Getting Started with Virtuoso ADE Explorer and Assemble…

By now, you have probably heard about the new family of Virtuoso ADE tools, publicly…

• 2 min read
Analog Design Environment , ADE XL , ADE , Virtuoso , IC6.1.7 , Custom IC Design

Analog/Custom Design

Welcome to the New Sound of Analog Design

The new Virtuoso ® ADE product suite enables designers to fully explore, analyze…

• 2 min read
CDNS - Fix Layout Hompage