Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

Did you know? Enriched schematic content available in PDF files from DEHDL (ConceptHDL…

For years, Concept-SCALD, and ConceptHDL (DEHDL) customers have been using various…

• 1 min read

RF Engineering

Measuring Transistor ft

So let’s consider a practical example of creating test benches and performing measurements…

• 5 min read
Measuring Transistor ft , RF design

System, PCB, & Package Design 

Shocking Technologies Becomes a Cadence Connections Member

In an announcement concurrent with Semicon West 2008, Shocking Technologies has …

• less than a min read
PCB Layout and routing , electrostatic discharge (ESD) dangers , Shocking Technologies , SPB , PCB design

Verification

C-to-Silicon Compiler Launch

On July 14th, Cadence introduced C-to-Silicon Compiler, a next-generation high-level…

• 1 min read
high-level synthesis adoption , C-to-Silicon Compiler

RF Engineering

Inductors On Demand, at least one RF design task can be really automated!

Inductors, transformers and transmission lines are critical components in any high…

• 1 min read
Virtuoso Spectre , Spectre RF , Virtuoso PCD , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design , Circuit Design , Virtuoso Passive Component Designer , wireless integrated circuit verification

Digital Design

Customer Experiences With Low-Power Design

Hello and welcome to the new Cadence community site, and my first blog post. You…

• 4 min read
Low-Power , Logic Design , Digital Implementation , The Power Forward Initiative

Verification

Emulation Drivers - A growing set of selection criteria

Some say that the growth of the emulation market in last few years was driven by…

• 2 min read
Acceleration , System Design and Verification , Emulation , Hardware/software co-verification

System, PCB, & Package Design 

What's Good About Differential Pair Support in ASA?

What's Good About Differential Pair Support in ASA? Quite a bit actually! In…

• 1 min read
ASA , Allegro System Architect (ASA) , PCB design , Differential Pair Support

Verification

The barriers to efficient System Level Design and Verification

The EDA industry been doing system level design and verification for years; we just…

• 1 min read
System Design and Verification

Verification

Verification Hierarchy of Needs

Verification consultant Brian Bailey recently started blogging for Chip Design Magazine…

• 2 min read
Verification planning and management , System Design and Verification , Run and Debug

Analog/Custom Design

Hello from the custom design corner of Cadence

Greetings! My name is Steve Lewis and I'm a product marketing director working in…

• less than a min read
Custom IC Design

Verification

The value of chaos (really!)

Ordinarily chaos is bad thing. Yet like it or not, t he world your SoC lives in is…

• 2 min read
Functional Verification

Digital Design

The Case for Robust Database Access

The most frequently viewed forum post in the old cdnusers.org "Digital IC->Floorplanning…

• 3 min read
First Encounter , Hierarchical Module Ports , robust data access , Digital Implementation , CTS

Verification

Why is OVM important for Specman/e customers?

With all of the press and interest from customers adopting it, I am sure most of…

• 2 min read
Verification methodology , Functional Verification , OVM , eRM

Analog/Custom Design

So, where is that mixed-signal behavioral model I ordered?

It has been said many time that SPICE, the analog engineers tool of choice, is virtually…

• 2 min read
Chip-level simulation , Electrical validation , Test , Block-level simulation , Virtuoso , AMS simulation , Circuit Design , Modeling , Custom IC Design

Verification

Report on the first OVM World Summit at DAC

At the recent Design Automation Conference (DAC) in Anaheim, Calif., Cadence did…

• 1 min read
DAC , Verification methodology , Functional Verification , OVM

System, PCB, & Package Design 

PakSi-E "ocho" fuels Cadence Package SI solutions

In case you haven't heard, Allegro Package SI and Cadence SiP SI solutions now work…

• less than a min read
Digital SiP design , IC Packaging & SiP design , SI analysis and modeling

System, PCB, & Package Design 

Xrosstalk talks AMI

There's a great issue of Xrosstalk magazine out there that talks about algorthmic…

• less than a min read
PCB Signal and power integrity , SerDes , PCB design

RF Engineering

Senrinotabi

Greetings! My name is Art Schaldenbrand and I have been at Cadence for 12 years supporting…

• less than a min read
RF design
CDNS - Fix Layout Hompage