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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

RISC-V Available in Silicon

One of the announcements at the recent RISC-V workshop was by SiFive . This is the…

• 4 min read
risc-v , freedom everywhere 310 , hifive1 , open source hardware , fe310 , open source , Arduino , Breakfast Bytes , sifive

Analog/Custom Design

Analog Design Resonance: Playing with Violation Filters

We'd like to welcome guest writer Yanyan Qiao from our Cadence Japan AE team. Many…

• 2 min read
Explorer , asserts , ADE XL , Virtuoso ADE , Assembler , device checks

Breakfast Bytes

RISC-V 5th Workshop Highlights

The fifth (V th ?) RISC-V workshop took place this week at Google in Mountain View…

• 5 min read
risc-v , codasip , risc-v foundation , isa , Breakfast Bytes , sifive

Breakfast Bytes

What's For Breakfast? Video Preview December 5th to 9th

https://youtu.be/IAPCDXodsno Monday: James Adams of the Raspberry Pi foundation…

• less than a min read
risc-v , Raspberry Pi , hifive1 , 5 nanometer , Chinese room , OrCAD , 5nm , computer consciousness , IEDM , sifive , computer thought , Allegro

Breakfast Bytes

The Internet of Space

At EDPS back in May (yes, I know I'm behind), Andrew Filo talked about Building the…

• 3 min read
kicksat-2 , EDPS , femto-satellite , space , NASA , internet of space , Breakfast Bytes

Verification

Creating Code from Tables

Some things are best described with tables—each column shows the values for one category…

• 6 min read
Specman , Tables , e , verification

Breakfast Bytes

Protium: FPGA Prototyping the Cadence Way

I attended a recent workshop on Protium titled Accelerating Embedded Software Development…

• 4 min read
TTP , Protium , FPGA prototyping , time to prototype , Breakfast Bytes , FPGA , verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Bluetooth 5: Making Mobile Connectivity Seamless in an IoT…

Tired of struggling with pairing your Bluetooth devices and getting them to work…

• less than a min read
Whiteboard Wednesdays , IoT , range limitations , bluetooth , Internet of Things , mobile , Bluetooth 5 , connectivity

Breakfast Bytes

Portable Stimulus Standard

There is an Accellera working group that is developing a portable stimulus standard…

• 7 min read
54dac , DVcon , Accellera , pss , Breakfast Bytes , portable stimulus standard

Breakfast Bytes

IEDM in December—7nm Announcements

Soon it is the International Electron Devices Meeting. It takes place in San Francisco…

• 4 min read
extreme ultra violet , iedm 2016 , IBM , Samsung , TSMC , GlobalFoundries , 7nm , EUV , IEDM

Breakfast Bytes

What's For Breakfast? Video Preview November 28th to December 2nd

https://youtu.be/CUGTiPJQjuI Monday: My preview of IEDM which includes 7nm…

• less than a min read
risc-v , IBM , 7 nanometer , Perspec , Protium , Samsung , TSMC , gf , risc-v workshop , iOS , FPGA prototyping , femto-satellite , GlobalFoundries , pss , internet of space , IEDM , portable stimulus standard

Breakfast Bytes

Happy Thanksgiving. Do You Have Toenailitis?

It’s Thanksgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

• 3 min read
bayes' theorem , physicians' knowledge of statistics , statistical literacy , false positive , false negative , turkey , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: ADE Explorer Setup - Save Now and Reuse Later!

Have you ever come across a situation where you have a test setup in ADE Explorer…

• 3 min read
Explorer , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , Virtuoso Video Diary , mixed signal

System, PCB, & Package Design 

Learning Advanced Flex and Rigid-Flex Design Support in Allegro 17.2-2016

Allegro PCB Editor now offers Rigid-Flex applications where it’s common to have different…

• 2 min read
Cadence Design Systems , PCB Editor , PCB design , Allegro PCB Editor , Allegro

Breakfast Bytes

Future of EDA: The Q & A

There was a recent panel discussion at Cadence on the future of EDA. The panelists…

• 4 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

Future of EDA: Industry...Well, Cadence...Weighs In

There was a recent panel discussion at Cadence on the future of EDA. If you didn…

• 3 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Breakfast Bytes

The Future of EDA: The View from Academia

There was a recent panel discussion at Cadence on the future of EDA. Of course the…

• 6 min read
Cadence Academic Network , Stanford , future of eda , Berkeley , Breakfast Bytes

Verification

A Personal History of Functional Verification

In my most recent blog post , I summarized some of the key points from an October…

• 4 min read
ASIC , uvm , pswg , formal. Verisity , Functional Verification , System Design and Verification , OVM , System Development Suite , constrained-random , Simulation acceleration , Accellera , metric-driven verification , Virtual Platforms , Hardware/software co-verification , simulation , FPGA , System Design and Verification

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Via Structures - The Next Generation High Speed…

Via transitions are very common for signals. And in high speed frequencies, these…

• 2 min read
diff pairs , Signal Intregrity , High Speed , PCB design , differential pairs , SI analysis and modeling , Differential Pair Support , Why Move Up to 17.2
CDNS - Fix Layout Hompage