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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

Verification

Unraveling the Newly Introduced Segmentation in PCIe 6.0

Overview The PCIe protocol evolved to its sixth generation in 2021, doubling its…

• 4 min read
verification strategy , Functional Verification , System Design and Verification , VIP , SoC , PCIe

カスタムIC／ミックスシグナル

Start Your Engines: ミックス・シグナルシミュレーションの効率を最適化する

Cadence Spectre AMS Designerは、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS , mixed-signal methodology , AMS Designer , Start Your Engines , AMSシミュレーション , ミックスシグナル手法 , AMS simulation , japanese blog

Digital Design

Training Insights – Why Is RTL Translated into Gate-Level Netlist?

Have you ever wondered how those tiny chips in your phone or computer actually work…

• 3 min read
Physical verification , conformal , Static timing analysis , DFT , EDI , Modus DFT , Tempus , Gate level simualtion , LEC , Signoff Analysis , DRC , STA , RTL-to-GDSII digital implementation digital design design verification Xcelium Verisium Genus Modus DFT Conformal Innovus Tempus Voltus Quantus , Floorplanning , RTL-to-GDSII , verisium , Xcelium Logic Simulator , Logic Design , Digital Implementation , Innovus , Timing analysis , Power Analysis , Synthesis , Placement , Quantus , Tempus Timing Signoff Solution , physical implementation , vManager , Modus ATPG , verification

Verification

Real Number Modeling Streamlines Mixed-Signal Verification

Semiconductor design is swiftly evolving, with mixed-signal design playing a pivotal…

• 4 min read
Functional Verification , Mixed Signal Verification , Xcelium Logic Simulator , Mixed-Signal , RNM , mixed signal , verification , EEnet

Corporate News

Switch – The AI, Cloud, and Enterprise Data Center Experts

Switch stands at the forefront as the premier data center designer, builder and operator…

• 1 min read
CFD , featured , switch , NVIDIA , digital twin , designed with cadence , Computational Fluid Dynamics , datacenter , Cadence Reality DC

Learning and Support

Compelling Profiles Drive Higher Engagement in Cadence Community Forums

You encounter an insightful discussion post, a suggested or verified answer within…

• 1 min read
PCB , CFD , Allegro X AI , Community , cadence , awr , Cadence Community Profile , Cadence Community Forums , SPB , PCB design

Computational Fluid Dynamics

From Sketch to Speedway: McLaren Formula 1 Team’s Aerodynamics Tale

Formula 1 is renowned for its avant-garde technology and engineering excellence.…

• 3 min read
CFD , featured , McLaren Racing , formula 1 , Aerodynamics

Life at Cadence

Exploring Strengths with Personality and Preference Inventory (PAPI) Assessment

Written by Pooja Pangoria, Software Engineering Group Director, Bangalore “You alone…

• 5 min read
Corporate Culture , personal development , life at cadence

カスタムIC／ミックスシグナル

Virtuoso Studio: Virtuoso ADE Assemblerでシミュレーション履歴に名前を付ける方法は？

当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ…

• less than a min read
カスタムIC , Virtuoso Analog Design Environment , japanese blog , Custom IC , Virtuoso ADE Assembler , ADE Assembler , IC23.1 , Virtuoso IC23.1

Corporate News

Socionext Is Tackling SoC Design Challenges

Socionext is an SoC company that has pioneered its business model to help companies…

• 1 min read
Tempus , designed with cadence , Socionext , digital , certus , Quantus

System, PCB, & Package Design 

Podcast: PCB 3.0: It’s All About the Data

Data management and PCB design discussions have shifted from the basics of data management…

• less than a min read
data management , Allegro Pulse , PCB design , Workforce Development , Allegro

Corporate News

Cyber Security at the Olympics: Protecting the World's Greatest Games

The Olympic Games are more than just an international sporting event. They symbolize…

• 7 min read
security , cloud , cyber attacks , cyber security , Olympics , 2024 Paris Olympics , technology

System, PCB, & Package Design 

System Analysis Knowledge Bytes - Importance of VRM Modeling in PDN Simulation

This post talks about the role of VRMs in Power Integrity (PI) analysis It discusses…

• 5 min read
Power Integrity Analysis , PDN , Cadence Online Support , Sigrity OptimizePI , signal integrity analysis , PDN Analysis , RAKs , Voltage Regulator Modules , VRMs

Corporate News

VIP Portfolio Expands for Data-Intensive Hyperscale Data Centers, HPC, and AI/ML

New additions, including first-to-market VIP for PCIe 7.0, Ethernet 1600G, GDDR7…

• 1 min read
ucie , Verification IP , featured , data center , VIP , PCIe 7.0 , PCIe , HPC , hyperscale , high-performance computing , AI/ML , GDDR7

Corporate News

Dream Chip and Cadence Demo Automotive SoC Featuring Tensilica AI IP at Embedded…

Cadence Verification and RTL-to-GDS Digital Full-Flow Tuned for Automotive Safety…

• 2 min read
Automotive , Verification IP , Tensilica , verification

System, PCB, & Package Design 

System Analysis Knowledge Bytes - Early System-Level Thermal Analysis

This post introduces you to the CAD capabilities of the Celsius Thermal Solver. It…

• 3 min read
Celsius Thermal Solver , Cadence Online Support , RAK , Celsius 3D , Thermal Analysis

Corporate News

The History of Electronics in Sports

In today's fast-paced world, technology touches nearly every part of our lives, including…

• 5 min read
featured , PSPICE , design excellence , Tensilica , 49ers , McLaren Racing , olympic , Olympics , AI , technology

Learning and Support

CadenceLIVE Silicon Valley 2024

CadenceLIVE Silicon Valley 2024 was a notable event recently held at the Santa Clara…

• 2 min read
digital design , Semiconductor , bridgingthelearninggap , cadencelive , online training

SoC and IP

Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence…

• 2 min read
Design IP , IP , featured , PHY , 128 GT/s , PCIe 7.0 , PCIe , Optics , SerDes , SerDes IP
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