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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Verification

OVM Metric Driven Verification With an FPGA-based Design

During the last 2 years I have enjoyed the opportunity to work with the Incisive…

• 2 min read
System Design and Verification , OVM , Incisive , System simulation and analysis , ISX , Hardware/software co-verification , FPGA

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 2

I keep my toothpaste in my bathroom. I keep the paprika in the kitchen. I keep the…

• 2 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

The DWARF Debugging File Format

The Chronicles of Narnia has always been one my favorite series of books. Today,…

• 7 min read
System Design and Verification , DWARF , ARM , ELF , debugging

Verification

Enabling OVM Transaction Debug in SimVision Without Code Changes

Are you tired of putting print statements in your code to do debug? Do you work…

• 5 min read
SystemVerilog , debug , Functional Verification , simvision , OVM SV , OVM 2.0 , IES , IES-XL

Verification

Team genIES Bloggers Create Simulation Magic

Simulation is a huge topic. Performance, debug, mixed-signal, low-power, assertions…

• 1 min read
Functional Verification , Incisive , OV , IES , IES-XL

Verification

Tips on Using “vhdlsync” With e+Mixed HDL Simulation

[ Team Specman welcomes Principal Support Application Engineer Avi Farjoun to share…

• 3 min read
AF , Specman , Functional Verification , tech tips , Incisive , e , Verilog , multi-language , Incisive Enterprise Simulator (IES) , VHDL , IES , IES-XL

Verification

Thoughts on the DVClub Talk: "Is it Time to Declare Verification War?"

As noted in a prior post , I had the pleasure of attending a DVClub talk given by…

• 2 min read
verification strategy , metric driven verification (MDV) , Functional Verification , DVClub , MDV

Analog/Custom Design

Things You Didn't Know About Virtuoso: Managing Your Real Estate - Part 1

Yeah, right...in this economy, don't talk to me about real estate. But I'm not talking…

• 3 min read
real estate , Virtuoso , assistants , Custom IC Design

Verification

Heads-up: Mixed Signal Verification Webinar (June 10)

For those Specmaniacs using the REAL number data type & ports capabilities in Specman…

• 1 min read
AMS , Specman , verification strategy , Functional Verification , Incisive , e , Incisive Enterprise Simulator (IES) , verification , IES-XL

RF Engineering

Join us at the Cadence booth at the International Microwave Symposium

If you listened to Tom's advice on this blog two months ago and registered for the…

• 1 min read
RFIC , Spectre RF , Virtuoso , RF design , International Microwave Symposium

Verification

New IntelliGen Statistics Collection Utilility

As noted in white papers , prior posts , and the Specman documentation, since IntelliGen…

• less than a min read
IEEE 1647 , IntelliGen , Specman , Functional Verification , Incisive , e , team specman , Incisive Enterprise Simulator (IES) , IES , IES-XL

Verification

Synthesis Really DOES Need to Change

A great article appeared in Chip Design a few weeks ago written by Tets Maniwa, …

• 2 min read
System Design and Verification , rtl compiler , C-to-Silicon Compiler

Analog/Custom Design

Things You Didn't Know About Virtuoso: Editing Properties

When I was growing up, my mother would usually bake a ham for Christmas dinner. She…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Digital Design

MarCom 2009 - New, Exciting, Educational

As a Marketing Communications professional, I am always looking for creative ways…

• 2 min read
EDI , EDI system , encounter digital implementation system , Digital Implementation

SoC and IP

The Great Escape, Part II: How These Companies Exited the DRAM Business

Case Histories of Significant DRAM Market Withdrawals : This article continues…

• 18 min read

Verification

Inside Cadence: "Stars & Strikes" charity event

Allow me to make a brief digression from EDA technology blogging to give you all…

• 1 min read
Functional Verification , charity benefit , Stars and Strikes festival

Verification

Where's the Bridge to Cross the Great Divide?

At this year's Embedded System Conference in San Jose there was a panel with the…

• 8 min read
windows , dwarfdump , VMware , Embedded Systems Conference 2009 , ISX , Hardware/software co-verification , linux

Verification

New "E" text editor and e templates

Imagine Team Specman's surprise when we came across this article on Slashdot about…

• 1 min read
IEEE 1647 , eclipse , Specman , Functional Verification , e , AMIQ , verification , IES-XL

SoC and IP

Denali MemCon leads "Memory Week" in Silicon Valley, June 22-25

Denali MemCon 2009, scheduled for the Santa Clara Hyatt Regency on June 22-24, is…

• 1 min read
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