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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

DDR4 Power-Aware Signal Integrity Adopting Serial Link Simulation Techniques

The signal integrity (SI) prophets had predicted this time would come, and it turns…

• 4 min read
Serial link analysis , DDR4 , BER Analysis , SystemSI , Power aware SI , Allegro Sigrity

Verification

Advanced Profiling for SystemVerilog, UVM, RTL, GLS, and More

The profiler helps to figure out the components or the code streams that take the…

• 2 min read
SystemVerilog , uvm , profiling , Incisive , post-simulation profiling , verification

SoC and IP

IoT Focus: Natural User Interface Design Crucial to Success

Each era of electronics innovation is generally marked by a dominant end application…

• 2 min read
Consumer Electronics , cadence , IoT , IP integration , IOT applications , ip cores , Internet of Things , Seow Yin Lim , interface design , user interface

Whiteboard Wednesdays

Whiteboard Wednesdays - How to Support Higher Performance Multimedia Applications…

In this week's Whiteboard Wednesdays, Charles Qi continues his discussion on hosted…

• less than a min read
Whiteboard Wednesdays , IP , hosted virtual desktop , user inputs processing , virtualized device enumeration , USB controllers , multimedia

System, PCB, & Package Design 

What's Good About Allegro DEHDL Net Renaming? The Secret's in the 16.6 Release!

Just a brief post this week to mention a new capability for Allegro Design Entry…

• less than a min read
Allegro Design Entry , Allegro 16.6 , 16.6 , SPB , Design Entry HDL , PCB design , Design Entry

Verification

Boost Efficiency and Performance of Simulation Acceleration Through New Rapid Adoption…

The state-of-the-art Palladium XP hardware/software verification computing platform…

• 2 min read
ICE , sim accel , IXCOM , Palladium XP , COS Cadence Online Support , Simulation acceleration , hsv , RAKs , stb

Whiteboard Wednesdays

Whiteboard Wednesdays - The Evolution of NAND Flash

In this week's Whiteboard Wednesdays, Lou Ternullo explains NAND Flash and the need…

• less than a min read
Whiteboard Wednesdays , IP , BCH algorithm , NAND flash , error correction

Verification

Verification IP: 7 Things I Learned By Browsing Cadence Online Support Last Mont…

Using proven Cadence Verification IP (VIP), you can verify SoC designs faster, more…

• 4 min read
Verification IP , IVD , Cadence app notes , MDIO Interface , VIP , Cadence Online Support , DpDm , SOMA to UVM Configuration

System, PCB, & Package Design 

Strengthen Your Plane-to-Plane Connections with Cadence 16.6 IC Package Shorting…

Manufacturability and quality of the power and ground feeds for your package are…

• 2 min read
SiP , IC Package , 16.6 , APD , package design , Allegro Package Designer

Verification

New VIP RAKs Help in Learning Integration of Ethernet GMII and M-PCIe into SystemVerilog…

There is always a demand for learning something simply and quickly on your own in…

• 3 min read
SystemVerilog , Verification IP , uvm , GMII , Rapid Adoption Kit , VIP , M-PCIe , RAK

Whiteboard Wednesdays

Whiteboard Wednesdays - Defining Different Types of USB Controllers

In this week's Whiteboard Wednesdays, Jacek Duda takes a closer look at different…

• less than a min read
Whiteboard Wednesdays , host , bus , USB controllers , peripheral devices , hub

SoC and IP

Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since…

• 1 min read
PCIe controller , PCIe IP , PCIe low power , PCIe , PCIe PHY

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

Cadence Online Support, https://support.cadence.com/ , provides access to support…

• 5 min read
COS , IMC , SystemVerilog , random stability , LPS , UVM-ML , CPF , debugging tips , Cadence Online Support , UVM ML , troubleshooting , irun , IES , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6…

Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region…

• less than a min read
constraint region , Allegro 16.6 , SPB , PCB Editor , BGA , Layout

Whiteboard Wednesdays

Whiteboard Wednesdays - Get to Know 802.11a/c Wireless Analog Front End Solution

In this week's Whiteboard Wednesdays, Priyank Shukla discusses Cadence's wireless…

• less than a min read
Whiteboard Wednesdays , wireless AFE , 802.11a/c , analog front end , AFE

SoC and IP

Ethernet in Cars - The Next Big Thing for Ethernet

Ethernet is coming to cars. Cars now have rear-view cameras and infotainment systems…

• 2 min read
CDNLive , Automotive Ethernet , automotive electronics , broadcom , Ethernet , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays - See How Customizable Processors Can Help to Offload Your…

In this week's Whiteboard Wednesdays, we take a little different approach and show…

• less than a min read
Whiteboard Wednesdays , IP , customizable processors , Tensilica , offload application processor

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Dual-Side Contact Components? It’s in the 16…

The use of dual-sided contact components when placed on internal layers of the PCB…

• 3 min read
PCB Layout and routing , Allegro GUI , inset vias , Allegro 16.6 , Routing , staggered vias , layer stacks , SPB , PCB Editor , PCB routing , Layout , via , PCB design , Allegro PCB Editor , buried vias , HDI , PCB Capture

Analog/Custom Design

EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia…

• 2 min read
DAC , Carnegie Mellon University , EDA , memory circuit yield , Semiconductor , university program
CDNS - Fix Layout Hompage