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Featured

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
KomalJohar 17 Dec 2025 • 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
Corporate 17 Dec 2025 • 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
Cadence Japan 15 Dec 2025 • less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
Corporate 11 Dec 2025 • 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Breakfast Bytes

CDNLive EMEA Eins

Every CDNLive has a little bit of a different structure. At CDNLive EMEA in Munich…

Paul McLellan 17 May 2017 • 7 min read
High-Level Synthesis , Automotive , Tom Beckley , CDNLive , CDNLive EMEA , iN7 , JasperGold , HLS , Breakfast Bytes

RF Engineering

7 Habits of Highly Successful S-Parameters: How to Simulate Those Pesky S-Parameters…

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic…

Tawna 16 May 2017 • less than a min read
S-parameter , Spectre RF , Spectre , International Microwave Symposium

Breakfast Bytes

JasperGold: Stepping up to RTL Signoff

When I was on my last tour of duty at Cadence in the early 2000s, we had a late afternoon…

Paul McLellan 16 May 2017 • 7 min read
Intel , Jasper , JasperGold , Formal verification

Breakfast Bytes

The New Tensilica Fusion G6 DSP

Only last week, in Are General-Purpose Microprocessors Over? I wrote about how general…

Paul McLellan 15 May 2017 • 4 min read
fusion G6 , Tensilica , Breakfast Bytes , digital signal processor

Computational Fluid Dynamics

Fluid Dynamics Simulation of a Generic Gas Turbine Combustor

This case study on combustion and radiative heat transfer in a generic gas turbine…

AnneMarie CFD 14 May 2017 • less than a min read

Breakfast Bytes

FD-SOI State of the Union: There's Supply—Is There Demand?

I went to the annual SOI Silicon Valley Symposium recently. As last year, they had…

Paul McLellan 12 May 2017 • 11 min read
dreamchip , China , NXP , 22fdx , 12fdx , Samsung , handel jones , GlobalFoundries , ARM , ibs , Breakfast Bytes , FD-SOI

Analog/Custom Design

Virtuosity: What's New in analogLib

It's been a while since analogLib was updated, so we decided to pay some attention…

Yagya Mishra 12 May 2017 • 4 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , ADE , Virtuoso , Analog Design Environment , Schematic Editor , Virtuosity , Custom IC Design , Schematic , ADE Assembler

Breakfast Bytes

RISC-V 6th Workshop 上海

The 6th RISC-V workshop was held in early May. It was the first one in Asia, at Shanghai…

Paul McLellan 11 May 2017 • 11 min read
computer architecture , risc-v , risc-v foundation , dave patterson

Breakfast Bytes

What's For Breakfast? Video Preview May 15th to 19th 2017

https://youtu.be/WTQhUyl2BBE Coming from Jing'an Park, Shanghai, China (camera…

Paul McLellan 10 May 2017 • less than a min read
Automotive , dreamchip , CDNLive , CDNLive Munich , Tensilica , software development

Breakfast Bytes

Are General-Purpose Microprocessors Over?

There is apparently a rule of thumb among journalists that when the headline of an…

Paul McLellan 10 May 2017 • 8 min read
Intel , risc-v , processor , MIPS , Tensilica , RISC , ARM , microprocessor , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - CNN Challenges: Compute Requirement

In this week's Whiteboard Wednesdays video, Megha Daga takes a deep dive into compute…

References4U 9 May 2017 • less than a min read
Whiteboard Wednesdays , convolutional neural networks

Breakfast Bytes

Soft Error Rates in Satellites and Cars

Space turns out to be an interesting area for semiconductors, especially looking…

Paul McLellan 9 May 2017 • 8 min read
Automotive , st microoelectronics , ser , soft error rate , cubesat , see , single event effect , seu , space , Breakfast Bytes , satellite

Breakfast Bytes

NASA: "Never Have Another Accident Due to Our Organizational Flaws"

The keynote at the IRPS reliability conference I attended was by Nancy Currie-Gregg…

Paul McLellan 8 May 2017 • 7 min read
space shuttle , NASA , Breakfast Bytes , reliability

Breakfast Bytes

TSMC @ N7 with Cadence

One presentation at the recent CDNLive Silicon Valley was about using Cadence tools…

Paul McLellan 5 May 2017 • 4 min read
Genus , Tempus , TSMC , n7 , Innovus , Quantus , Breakfast Bytes

Analog/Custom Design

Virtuoso Video Diary: How Can I Plot or Evaluate with the New Expression Builder…

Indeed, the new Expression Builder has made expression creation much easier, but…

Arja H 5 May 2017 • 3 min read
Analog Design Environment , evaluateADE Explorer , Analog Simulation , plot , expressions , analog , Mixed-Signal , Expression Builder , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design , calculator

Breakfast Bytes

UVM Is Now IEEE 1800.2 and There's a Ten-Year Story to That

UVM, the Universal Verification Methodology, just became IEEE 1800.2-2017. I wondered…

Paul McLellan 4 May 2017 • 6 min read
SystemVerilog , Superlog , ieee 1800.2 , uvm , Accellera , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview May 8th to 12th 2017

https://youtu.be/sIFo4JKjVxw Coming from NASA Ames Research Center, Sunnyvale…

Paul McLellan 3 May 2017 • less than a min read
space shuttle , risc-v , NXP , ser , 22fdx , soft error rate , 12fdx , Samsung , single event upset , Tensilica , single event effect , ST Microelectronics , GlobalFoundries , ARM , microprocessor , NASA , reliability , FD-SOI

Breakfast Bytes

Bayern München Will Not Be at CDNLive Munich: Here's What They Will Miss

Yes, it's true. After attending CDNLive EMEA for the last couple of years, Bayern…

Paul McLellan 3 May 2017 • 3 min read
Automotive , NXP , Munich , CDNLive , CDNLive EMEA , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays – Introduction to Cadence Tensilica Vision C5 DSP

In this week's Whiteboard Wednesdays video, Pulin Desai describes the main features…

References4U 2 May 2017 • less than a min read
Whiteboard Wednesdays , Vision DSP , convolutional neural networks , CNN
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