Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Hit The Road - DAC!

OK, now that the Design Automation Conference (DAC) seems to be rotating among San…

• 1 min read
DAC , uvm , Functional Verification , OVM

Verification

Snapshots From Day 0 of DAC 2010

Below are some snapshots of some "day 0" events, and last minute DAC preparations…

• less than a min read
DAC , uvm , OVM , Palladium XP

Verification

Advanced Option Brings New Features to Specman/e Users

Great news for Specmaniacs -- a new Specman Advanced Option is being announced at…

• 1 min read
SystemVerilog , DAC , Specman , Functional Verification , Multi-Core , e , team specman , specman elite , Incisive Enterprise Simulator (IES) , IES-XL

SoC and IP

MemCon 2010 registration closing in on 400 attendees. Theme is "Roadmap: GHz DDR3…

We’re still more than a month away from MemCon 2010 in Santa Clara (July 28) and…

• 1 min read

Verification

A New Toy for UVM Geeks

Wasn't it great when you were a kid at Christmas, and you got all those new toys…

• 1 min read
SystemVerilog , methodology , Verification methodology , metric driven verification (MDV) , Functional Verification , Incisive , MDV

SoC and IP

Questions for the DAC Pavilion Panel on multicore design

As I wrote yesterday, I’ll be chairing a Multicore panel at DAC in Anaheim on Monday…

• 1 min read

Verification

Cadence Contributes ESL Methodology To TSMC Reference Flow 11

The EDA360 industry vision document shows how growing complexity and application…

• 3 min read
ECO , OIP , C to Silicon , TSMC , system , ESL , verification

SoC and IP

Don’t miss the multicore Pavilion panel discussion at DAC on Monday, June 14

I’ll be moderating the Pavilion panel titled “The Multiplier Effect: Developing Multi…

• less than a min read

SoC and IP

Denali to demo new PureSpec 2.0 verification-management technology at DAC 2010

This news is a bit far afield for Denali’s Memory Blog, but many of our blog readers…

• 1 min read

SoC and IP

Making SSDs, the TweakTown video: See how A-DATA makes SSDs based on SandForce SF…

TweakTown’s crew visited A-DATA’s manufacturing floor during Computex in Taiwan and…

• 1 min read

SoC and IP

ST Microelectronics’ SPEAr1300 Embedded Processor family employs Denali Databahn…

Last month, this blog described the new SPEAr1300 Embedded Processor family from…

• less than a min read

Verification

Accelerating Metric-Driven Verification With “Hotswap” on Verification Computing…

For a while now, Cadence has been providing leading verification solutions and methodologies…

• 1 min read
emulator , DAC , Acceleration , Palladium , hotswap , Emulation , hot swap , metric , metric-driven verification , MDV

Analog/Custom Design

ARM And Cadence Get To The “Core” Of Mixed-Signal Design

An increasing number of analog and mixed-signal designs in automotive, power management…

• 4 min read
Cortex , analog , Mixed-Signal , Virtuoso , Cortex-M0 , mixed signal , ARM

Verification

Specman, e, and EDA360

The EDA industry is all abuzz over the new vision paper "EDA360 - The Way Forward…

• 5 min read
SystemVerilog , DAC , AMS , uvm , Specman , IP , HW/SW , methodology , CDNLive , metric driven verification (MDV) , Functional Verification , VIP , EDA360 , Mixed Signal Verification , Multi-domain verification: HW/SW co-verification , Incisive , e , OVM-e , ISX (Incisive Software Extensions) , ClubT , Aspect Oriented Programming , SystemC , ISX , MDV , Incisive Enterprise Simulator (IES) , VHDL , ESL , AOP , Matlab , IES-XL , Trailblazer

SoC and IP

MemCon 2010 agenda posted. Your only problem: Which free track do you need to attend…

We’ve just posted the agenda for MemCon 2010. If you touch semiconductor memory in…

• 2 min read

SoC and IP

Apple controls 20% of NAND Flash market with iPhone and iPad says DRAMeXchange

With Apple fervor pheromones still heavy in the air from yesterday’s introduction…

• less than a min read

Verification

India Takes The Lead By Hosting The First Two “ClubTs” in 2010

Specman/ e users in India were very excited to see the first two ClubT events hosted…

• 4 min read
IntelliGen , Specman , Functional Verification , validation , e , team specman , ClubT , AOP , IES-XL

Verification

System Development – What To See At DAC 2010

The EDA360 vision paper specifies key System Realization challenges. Embedded software…

• 6 min read
DAC , cadence , ITRI , system realization , OSCI , Calypto , TSMC , Gary Smith , Imperas , SystemC , ARM , wind river , HLS , DAC 2010

SoC and IP

INDILINX reveals use of its Barefoot SSD controller in HLDS’ HyDrive optical/solid…

This blog has twice written up the newly announced HyDrive optical/solid-state hybrid…

• less than a min read
CDNS - Fix Layout Hompage