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Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella
cdns - all_blogs_categories

Blog - Post List

Latest blogs

System, PCB, & Package Design 

BoardSurfers: Four Reasons to Use Allegro ECAD-MCAD Library Creator

The Cadence  Allegro  ECAD-MCAD Library Creator helps you easily synchronize ECAD…

• 3 min read
Library Creator , 17.4-2019 , ECAD-MCAD Library Creator , PCB design

System, PCB, & Package Design 

IC Packagers: An Introduction to Allegro Package Designer Plus in 17.4

Some of you are APD users, building single-chip or non-stacked multi-chip packages…

• 5 min read
17.4 , APD , SiP Layout

Breakfast Bytes

What's Happening in RISC-V Land?

Last week was IEDM, the International Electronic Devices Meeting. I will write about…

• 5 min read
Western Digital , risc-v , NVIDIA , risc-v summit , Samsung , Qualcomm

System, PCB, & Package Design 

DATA Pulse: Speed up ECAD Part Search in Allegro System Capture

Do you often search for parts when creating Allegro System Capture projects? Yes…

• 2 min read
Cadence Design Systems , Library and design data management , PCB design , Allegro System Capture , Part Search

Breakfast Bytes

The Most Important Operating System Ever

I wrote recently about Brian Kernighan's memoir and history in Brian Kernighan's…

• 7 min read
android , unix , iOS , MacOS , linux

Academic Network

2019 Workshop on Electronic Design Automation in Hsinchu Taiwan

The Cadence Academic Network has been supporting the Workshop on Electronic Design…

• 1 min read
university , Taiwan , Cadence Academic Network , academic workshop , academia , university program

PCB、IC封装：设计与仿真分析

图文详解：如何在PowerSI中为封装体上添加假性球体和参考层？

本文由Cadence经销商之一的北京耀华创芯电子科技有限公司整理撰写。耀创科技专注于电子设计自动化（EDA）服务，在引进国外先进EDA工具的同时，针对中国市场特殊性…

• less than a min read
SI , Chinese blog , 中文 , Sigrity , IC封装 , S参数 , PowerSI

Breakfast Bytes

Known Good Die

Do you know what known good die are? Do you know what wafer sort is? Final test?…

• 6 min read
system-in-package , kgd , 3DIC , known good die

Breakfast Bytes

Brian Kernighan's Memoirs

If you have ever worked on placement or floorplanning, and probably some other areas…

• 7 min read

Breakfast Bytes

System in Package, Why Now? Part 2

This post is a continuation of last week's post Multiple Die in Packages. Why Now…

• 6 min read
3DIC , more than Moore , moore's law

Analog/Custom Design

Virtuoso IC6.1.8 ISR8 and ICADVM18.1 ISR8 Now Available

The IC6.1.8 ISR8 and ICADVM18.1 ISR8 production releases are now available for download…

• 2 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , IC Release Announcement blog , Virtuoso RF , Virtuoso Custom Placer , Electromagnetic analysis , Virtuoso , CLE , IC Release Blog , Custom IC Design , Virtuoso Layout Suite , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL , clarity

System, PCB, & Package Design 

IC Packagers: Copy and Paste Refresh in 17.4

The most common operations in any tool are probably adding, moving, deleting… plus…

• 3 min read
allegro 17.4 , APD , Allegro Package Designer , Allegro

Breakfast Bytes

Cadence at CES 2020: Tensilica Everywhere

Once again, Cadence will be at CES in Las Vegas. It takes place January 7 to 10,…

• 4 min read
CES , Tensilica

Analog/Custom Design

Virtuoso Meets Maxwell: Help with Electromagnetic Analysis - Part IV

This is the fourth blog in the multi-part series that aims at providing in-depth…

• 11 min read
AXIEM , SiP , ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Package Design in Virtuoso , Electromagnetic analysis , RF design , method of moments , Finite Element Method , Layout Editing , Allegro , clarity

Breakfast Bytes

Xcelium Is 50% Faster on AWS's New Arm Server Chip

At Re:invent, Amazon AWS announced Graviton 2, their second-generation Arm server…

• 3 min read
annapurna labs , nitro , cloud , aws , graviton 2 , cadence cloud , neoverse , ARM

定制IC芯片设计

Virtuosity: 针对高阶工艺节点器件级布线的工具— 干线-干线网状布线工具

本博客强调了干线-干线网状布线功能的重要性，它不仅为定制器件级的布线提供了解决方法，还提高了版图设计师们的工作效率.

• less than a min read
trunk mesh routing , Trunk generation , Interactive Routing , Chinese blog , Pin to Trunk , Cadence blogs , structured routing , ICADVM18.1 , Virtuoso Space-based Router , mesh routing , Layout EXL , trunk-to-trunk mesh , Layout Suite , trunk creation , Generate Trunk , mixed signal , Finish Trunk , EM Trunk Optimization , Custom IC Design , Virtuoso Layout Suite , Custom IC

Verification

Cashing the PSS Promises

A little bit of everything in the blog today: PSS is All Over As someone that was…

• 1 min read
uvm , CDNLive , Acceleration , virtual prototypes , Perspec , perspec system verifier , Emulation , DVcon , Accellera , System Design & Verification , pss , portable stimulus , verification

Breakfast Bytes

Sunday Brunch Video for 8th December 2019

https://youtu.be/3gP0Z02MVps Made at Salinas River State Park (camera Carey Guo…

• less than a min read
sunday brunch

Breakfast Bytes

System in Package, Why Now?

At HOT CHIPS this summer, one of the things I noticed was just how many of the designs…

• 6 min read
chiplet , 3DIC , more than Moore , moore's law
CDNS - Fix Layout Hompage