Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Fortune & Great Place To Work Name Cadence to 2025 World’s Best Workplaces List

Great Place To Work® and Fortune magazine have honored Cadence as one of the Fortune…

Corporate
• 2 min read
news story , Culture , featured

Corporate News

Spectre FX Simulator Cuts Intrinsic Semi’s Memory Verification Time by 4X

Intrinsic Semiconductor Technologies, a company transforming the semiconductor industry…

Corporate
• 2 min read
newstory , featured , spectre fx , Instrinsic Semi , verification

Corporate News

Cadence Welcomes ChipStack

ChipStack, a leading startup providing agentic AI solutions for chip verification…

Corporate
• 1 min read
featured , agentic ai , Xcelium Logic Simulator , AI-Driven Verification

SoC and IP

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY
cdns - all_blogs_categories

Blog - Post List
Latest blogs

CFD（数値流体力学)

チュートリアル火曜日 - メッシングを学ぼう

今日はただの火曜日ではなく、チュートリアルの公開日です。 我々のチュートリアルビデオをご存じですか？ 毎週火曜日は、 PointwiseのYouTubeチャンネル…

• less than a min read
CFD , video , tutorial , Computational Fluid Dynamics , japanese blog , Mesh Generation

CFD（数値流体力学)

今週のCFD

今週のCFDニュースには、今週の画像と今週のアプリケーションの両方が掲載されていますが、ご自身で結論を出してください。まだまだオンラインイベントが多いですが、AIAA…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics , japanese blog

System, PCB, & Package Design 

BoardSurfers: Training Insights: Tips to Zoom and Pan Efficiently in Allegro PCB…

While designing a layout within Allegro® PCB Editor, designers zoom in and out or…

• 4 min read
PCB , 17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

Breakfast Bytes

Cadence and Intel Demonstrate CXL 1.1/2.0 Interoperability

This weekend, timed to coincide with SC21, Cadence and Intel published a white paper…

• 6 min read
CXL , Intel , interoparability , cxl 2.0 , interop

PCB、IC封装：设计与仿真分析

详解有限元模型在系统分析中的应用

本文要点: 有限元分析是在复杂几何中为微分方程求解的一种基本的数值计算方法。 这些复杂的系统可能无法人工求解，而且可能存在不同物理现象之间的耦合，特别是在电子领域…

• less than a min read
Chinese blog , FEM , 多物理场 , 中文 , 电磁仿真 , 系统分析 , 多物理场仿真 , EM , 有限元 , 智能系统设计 , Clarity 3D Solver , 场求解器 , clarity

Computational Fluid Dynamics

This Week in CFD

As we stand on the precipice of another weekend (the weekend just means there are…

• less than a min read
CFD , Marine Engineering , Pointwise , Computational Fluid Dynamics , Omnis

Breakfast Bytes

Datapath Formal Verification 101: Technology and Technique

Earlier this week, Cadence announced the Jasper C2RTL App, which I covered in my…

• 7 min read
Jasper User Group , JUG , c2rtl , formal , datapath , Formal verification

System, PCB, & Package Design 

BoardSurfers: How to Map CAD Models in 3D Canvas

In the world of PCB design, shorter delivery deadlines have less scope of re-spin…

• 4 min read
PCB , 17.4 , BoardSurfers , MCAD , 3D Canvas , PCB Editor , 17.4-2019 , PCB design , CAD , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuosity: Virtuoso Design Intent Notes Now Speak Many Languages

Starting with ICADVM20.1 ISR20, you can write Design Intent notes in languages that…

• 2 min read
Virtuoso Design Intent , Virtuoso Schematic XL , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , ICADVM20.1 , Constraints , design intent , Custom IC Design , Custom IC , Virtuoso Layout Suite XL

Breakfast Bytes

Happy 10th Birthday ISO 26262

Today is the 10th anniversary of ISO 26262. It was first published on 11th November…

• 3 min read
Automotive , functional safety , midas , ISO 26262

Breakfast Bytes

Announcing Jasper C2RTL App: Formal for Algorithmic Designs

Today is the first day of the Jasper User Group (unofficially known as JUG to attendees…

• 2 min read
Jasper User Group , c2rtl , formal , Jasper , JasperGold

定制IC芯片设计

Virtuoso Meets Maxwell: 标准库组件的定义

The Allegro Package Designer 产品线提供IC 封装从创意到生产所需的一切，它可以从Virtuoso环境通过Virtuoso MultiTech…

• 1 min read
Libimport , Unified Library , JEDEC , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Virtuoso MultiTech , Package Design in Virtuoso , Allegro Package Designer Plus , Allegro Package Designer , die , Virtuoso , ICADVM20.1 , Cadence SiP Layout , Custom IC Design , Custom IC , Allegro , Chinese blogs , VMM

PCB設計／ICパッケージ設計

BoardSurfers: Allegro PCB Editorを17.4-2019 Hotfix 019以上にバージョンアップするべき理由とは

Cadence OrCAD and Allegro 17.4-2019 Hotfix 019（17.4-QIR3） は7月中旬にリリースされました。、現在は更に新しいHotfixがダウンロード可能です…

• 1 min read
PCB , 17.4 , BoardSurfers , PCB Editor , 17.4-2019 , 17.4-2021 , japanese blog , Allegro PCB Editor , 17.4-QIR3 , Allegro

Breakfast Bytes

Last-Mover Advantage

I was reminded recently of a video/transcript that I remember coming across when…

• 6 min read
startups , tesla , peter thiel

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Sigrity X the Next-Generation Signal and Power Integrity…

Explore how Sigrity X, the next-generation signal and power integrity (SI/PI) solution…

• 5 min read
Sigrity and Systems Analysis , Celsius Thermal Solver , SPEEDEM , XcitePI , Sigrity X , Voltus IC Power Integrity Solution , IBIS Modeling , Sigrity PowerSI , Power Integrity , Sigrity OptimizePI , IBIS-AMI , Signal Integrity , Sigrity SystemSI , Sigrity XtractIM , Sigrity PowerDC , Clarity 3D Solver , T2B , Allegro PCB Designer

Digital Design

Voltus Voice: Hierarchical Power Integrity Analysis—Everything You Need to Know About…

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss…

• 5 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Breakfast Bytes

Reality in Your Glasses

Despite all the recent noise about the Metaverse (and Facebook changing its company…

• 5 min read
rayban , Facebook , virtual reality , augmented reality , meta

中文技术专区

持续推进摩尔时代的IC设计艺术

2021 年 11 月 3 日，由 ASPENCORE 主办的“2021 全球高科技领袖论坛 - 全球 CEO 峰会&全球分销与供应链领袖峰会”于深圳举行。Cadence…

FormerMember • less than a min read
3D IC , Integrity , moore's law

The India Circuit

Mentor Story: Rajesh Swami Narayanan - Cadence Scholarship Program

The Cadence Scholarship Program is the flagship CSR program of Cadence India, introduced…

• 2 min read
CadenceCares , CadenceScholarshipProgram , cadence , Cadence India
CDNS - Fix Layout Hompage