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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Academic Network

2017 Workshop on Electronic Design Automation in Tainan Taiwan

It was the third continuous year that Cadence Academic Network supported the Workshop…

• 1 min read
Taiwan , Cadence Academic Network , EDA

Breakfast Bytes

Greg Yeric and Rob Aitken Dive into the Details

The last day of TechCon had two keynotes rich in deeper technical content, from Greg…

• 6 min read
security , greg yeric , graphen , IoT , trillion devices , Rob Aitken , more than Moore , moore's law , power

Breakfast Bytes

Advanced Packaging Delivers More Than Moore

Moore's Law is running out of steam. Depending on your point of view, it is dead…

• 8 min read
FOWLP , advanced packaging , 3DIC , Virtuoso , OrbitIO , Innovus , 2.5D , Allegro

Digital Design

Get Early Silicon Learning to Accelerate Yield Ramp-up

How important is it for your advanced node products to get early silicon learning…

• 2 min read
DNA , pattern analysis , machine learning , silicon learning , yield , test chip , design for manufacturing , DFM

Whiteboard Wednesdays

Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural…

• less than a min read
Whiteboard Wednesdays , neural networks

Analog/Custom Design

Virtuosity: Can I Plot Signals with Different Axis Units in the Same Window?

Have you been frustrated trying to drag signals around in Virtuoso Visualization…

• 1 min read
virtuoso visualization and analysis , Virtuoso Analog Design Environment , Analog Design Environment , ViVA

Breakfast Bytes

Supercomputers

HPC, or high-performance computing, is one of the big focus areas for semiconductors…

• 9 min read
Intel , top 500 list , top500 , supercomputer

Analog/Custom Design

Virtuosity: CDNLive India—Our Window to KYC!

In line with the recently-implemented mandate in India requiring banks and financial…

• 1 min read
CDNLive India 2017 , Cadence Help Future , Virtuosity , Virtuoso Video Diary , Cadence Help 3.0

Breakfast Bytes

What's For Breakfast? Video Preview December 11th to 15th 2017

https://youtu.be/Ar98HS9Dnow Coming from Union Square, San Francisco (camera Carey…

• less than a min read
government , risc-v , International Electron Devices Meeting , cots , risc-v workshop , Aviation , IEDM

SoC and IP

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

• 1 min read

Breakfast Bytes

Formal Verification Sign-Off...and the First Text Message

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 8 min read
Jasper User Group , JUG , formal , Oski Technology , Formal verification

RF Engineering

How to Set Up and Plot Large-Signal S Parameters?

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and…

• 1 min read
RF Simulation , Spectre RF , Virtuoso ADE , Virtuoso

Verification

Perspec System Verifier is #1 in Portable Stimulus in 2017 User Survey

It’s now official: Perspec System Verifier is rated the #1 product in the #1 category…

• 3 min read

Breakfast Bytes

Silexica: Mastering Multicore

Since the invention of the microprocessor, it was a dream that it would be possible…

• 9 min read
silexica , Tensilica , multicore

Breakfast Bytes

Jasper User Group: How to Be a Formal Verification Lead

Recently, it was the 10th annual Jasper User Group meeting (see my earlier post Jasper…

• 7 min read
Intel , Jasper User Group , JUG , formal , verification

RF Engineering

Triple Beat Analysis: What, Why & How?

The Triple Beat analysis is similar to Rapid IP2/IP3 analysis except that it uses…

• 2 min read
Virtuoso ADE , Virtuoso , Spectre , RF design

The India Circuit

Hello, My Name Is Anna. Can I Help You?

Chatbots are annoyingly familiar to anyone who has shopped online. The distracting…

• 3 min read
chatbot , artificial intelligence , Wysa , AI

Verification

Check Again: Cadence Announces Release of the First PCIe 5.0 VIP—With TripleCheck…

On November 28, 2017, Cadence announced the release of the first available PCIe®…

• 1 min read
Functional Verification , PCI-e , announcement , TripleCheck

Breakfast Bytes

Chips and Technologies: The First Fabless Company

As part of writing Fabless: the Transformation of the Semiconductor Industry a couple…

• 5 min read
fabless , chips and technologies , foundry
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