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SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Corporate News

Cadence at the TSMC OIP: Pioneering the Future of Semiconductor Design

The semiconductor industry stands at a pivotal moment. As we push toward more advanced…

Corporate
• 3 min read
OIP , featured , 3D-IC , 3DIC , TSMC

Corporate News

Building a Future Beyond Boundaries with Honda and Cadence

We at Cadence are proud to be a long-term partner of Honda R&D (HGRX), and our collaboration…

Corporate
• 6 min read
Automotive , featured , physical ai , automotive electronics , AI

Corporate News

CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI
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Blog - Post List

Latest blogs

Digital Design

Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal…

No matter how your name is spelt in different countries, and how they say it, once…

FormerMember • 1 min read
digital badge , conformal , training bytes , online training

PCB、IC封装：设计与仿真分析

如何建立一个数据中心：全靠 SerDes和散热

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “How to Build a Data Center…

• less than a min read
Chinese blog , 热分析 , celsius , 以太网 , PCIe , 中文 , 系统分析 , SerDes , 散热 , 数据中心

Digital Design

Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)?…

• less than a min read
Genus , gui , place and route , highlighted objects , physical implementation

Breakfast Bytes

An Interview with Morris Chang

A couple of weeks ago, Morris Chang, the founder of TSMC and, for a long time (twice…

• 4 min read
TSMC , Morris Chang

System, PCB, & Package Design 

ASCENT: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro Pulse

HotFix SPB17.40.028 of 17.4-2019 of Allegro® Pulse is out and is available for download…

• 5 min read
collaboration , data platform , Team design , QIR4 , 17.4-2019 , Allegro Pulse , Allegro System Capture , ASCENT

PCB、IC封装：设计与仿真分析

AWR：智能射频设计

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “ AWR: Intelligent RF Design…

• 1 min read
射频 , 5G , RF , 微波 , Chinese blog , awr , 中文 , awr v16

Breakfast Bytes

A History of Cadence in the Cloud

Cadence Cloud started before there even was a cloud. We just didn't call it Cadence…

• 7 min read
cloud , special post , cadence cloud

Verification

Enflame Accelerates the DFT and DFD Verification using Palladium

DFT (Design for Testability) provides the much-needed support to the manufacturers…

• 5 min read

System, PCB, & Package Design 

This Month in IDA

This month the In-Design Analysis (IDA) team kicked off its new blog program with…

• 1 min read
in-design analysis , Signal Integrity , electromagnetic , microwave design , thermal

PCB、IC封装：设计与仿真分析

OMNIS – 如何在汽车领域应对当今和未来的多物理场仿真挑战？

本文作者：Yannick Baux, Cadence产品研发总监 space 汽车行业一直使用 CFD 工具来设计和优化车辆的各个方面，从外部空气动力学到降噪，再到热管理…

• less than a min read
CFD , Chinese blog , 网格生成 , 流体力学 , 计算流体动力学 , CFD应用 , 仿真 , 中文 , 系统分析 , 汽车 , 多物理场仿真 , Omnis

Academic Network

Virtuoso Education Kit Available Now

The Cadence Education Kit initiative runs at full steam! After the release of the…

• 2 min read
Cadence Academic Network , Education Kit , Virtuoso , analog design

Breakfast Bytes

Always On at D&R

At the recent D&R IP-SoC Day 2022, Amol Borkar presented Designing the Next Ultra…

• 5 min read
always on , vision p1 , Tensilica , aon

PCB、IC封装：设计与仿真分析

如何在PCB设计中进行DDR布线？

DDR布线技术的重要性 在如今的印刷电路板设计中，双数据速率（DDR）存储器非常普遍。许多设计都会用到DDR存储器配置的不同版本，这需要在布局中使用特定的布线模式…

• less than a min read
Chinese blog , 布线 , PCB设计 , 中文 , DDR , Allegro PCB Editor , Allegro

Breakfast Bytes

ESD Alliance CEO Outlook 2022

Last week was the ESD Alliance CEO Outlook. It was hosted by Keysight (fka Agilent…

• 13 min read
keysight , cadence , ceo outlook , Siemens , ARM , D2S , esd alliance

Verification

How AMBA CHI Specification Has Evolved - CHI-E (r)evolutionary?

We covered CHI specification revisions A to D in my previous article , what about…

• 2 min read
Verification IP , Functional Verification , VIP , AMBA , CHI VIP

PCB、IC封装：设计与仿真分析

详解时域瞬态分析技术

本文要点： 所有的物理系统在运行动态中都会表现出一些瞬态行为，电子产品也是如此 瞬态分析技术可以帮助了解不同电气状态之间的转换 当检查测量数据或软件仿真数据时…

• less than a min read
Chinese blog , 时域 , 仿真 , 中文 , 系统分析 , Sigrity , 信号完整性 , 瞬态

The India Circuit

SemiconIndia 2022 Conference: A First-of-Its-Kind

The Ministry of Electronics and Information Technology (MeitY) organized a unique…

• 3 min read
Government of India , digital india , National Policy on Electronics , SemiconIndia 2022

Breakfast Bytes

Gabrièle Saucier on the History of IP

Recently, it was D&R's IP-SoC Silicon Valley 2022. The opening keynote was given…

• 4 min read
IP , ip-soc , d&r , semiconductor IP

Computational Fluid Dynamics

Fidelity CFD Overset Meshes to Simulate Rotor Hub Vortex Shedding in Helicopters

Vortex shedding in a helicopter rotor hub can be analyzed and captured precisely…

• 3 min read
CFD , drag prediction , Meshing Monday , vortex shedding , overset meshing , Pointwise , helicopter , rotor hub , Fidelity CFD , engineering , simulation software , NUMECA , Meshing
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