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Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology

Analog/Custom Design

Virtuoso Studio IC23.1 ISR16 Now Available

Virtuoso Studio IC23.1 ISR16 production release is now available for download.

Virtuoso Release Team
• 2 min read
IC 23.1 , featured , Virtuoso Studio , IC Release , Virtuoso

SoC and IP

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Being a Part of Something Truly Remarkable - UVM

For just over two years I have had the honor of playing a role in a dramatic example…

• 2 min read
uvm , Functional Verification , EDA360 , Incisive , Accellera VIP TSC , synopsys , IES , Mentor

Verification

The Tale of the Silicon Re-Spin and the Bug That Got Away

I'd like to continue my blog series discussing corner-case conditions of various…

• 4 min read
conformal , corner cases , clock domain crossings , CDC , bug , FIFO

Digital Design

Evolution of Design Exploration and Planning

The great architect Frank Lloyd Wright once said "you can fix it on the drafting…

• 2 min read
EDI , First Encounter , EDI system , partitioning , Floorplanning , encounter digital implementation system , Encounter Digital Implementation , Digital end-to-end flow , Floorplanning and Prototyping

Digital Design

Guest User Blog: dbShape For All Your Logical Operation Needs

This is a guest post from Jason Gentry at Avago. I hope you enjoy this useful piece…

• 4 min read
EDI , Avago , encounter , EDI 10.1 , dbShape , db access , Digital Implementation , Gentry , logical operations , tcl

System, PCB, & Package Design 

What's Good About Allegro Router and Highlighting? You’ll need the SPB16.3 Release…

Just a quick post this week on a new Allegro PCB Router feature in the SPB16.3 release…

• less than a min read
PCB , SPB16.3 , blind vias , Routing , specctra , Allegro 16.3 , layer stacks , SPB 16.3 , PCB Editor , Layout , via , design , "PCB design" , PCB design , highlighting , Allegro PCB Editor , buried vias , Allegro

Verification

The Role of Coverage in Formal Verification, Part 3

.special { font-family: 'Courier New' !important; } In the last post of this…

• 5 min read
ABV , methodology , verification strategy , coverage , metric driven verification (MDV) , Functional Verification , Formal Analysis , Model-checking , formal , Coverage-Driven Verification , Incisive , SVA , PSL , metric-driven verification , coverage driven verification (CDV) , assertions , IEV , simulation , IFV

Verification

Why the Demand for Acceleration and Emulation is Growing

The dream of any marketer is a growing demand for its product line. Let me start…

• 3 min read
emulator , ASIC , Acceleration , virtual platform , System Design and Verification , OVM , Palladium , Low power verification and analysis , Emulation , virtual prototype , System Design & Verification , Hardware/software co-verification , simulation , verification

System, PCB, & Package Design 

Shorter, Predictable Design Cycles (SPDC) – Ensuring Critical Signals Have a Return…

This is third in the series of blog posts about making your design cycles predictable…

• 2 min read
PCB , DDR2 , High Speed , webinar , PCB design , return path , PCI Express , SATA , Standards based Interfaces , DDR3 , Allegro

Analog/Custom Design

Analog Assertion Based Verification Methodology – Reality or a Dream? (Part 2)

The design and verification methodology for analog circuits has not changed much…

• 3 min read
ABV , assertion-based , Analog Simulation , analog , SoC , Mixed-Signal , SVA , PSL , AMS simulation , assertions , mixed signal , wreal , Custom IC Design , verification

System, PCB, & Package Design 

What's Good About Allegro Measure, Grids and Formulas? See For Yourself in SPB16

This week, I’m tossing together a mix of a few new SPB16.3 Allegro PCB Editor features…

• 2 min read
grids , PCB , PCB Layout and routing , Allegro 16.3 , SPB 16.3 , SPB , formulas , PCB Editor , High-Density Interconnect , Layout , via , design , PCB design , Allegro PCB Editor , Cline change , HDI , microvia , Allegro

Analog/Custom Design

Advanced Mixed-Signal Designs Demand a Unified Methodology

Mobile, automotive, consumer and medical applications require the productive realization…

• 4 min read
conformal , RF , mixed-signal seminars , Low Power , CPF , abstraction , analog , ECOs , Mixed-Signal , Convergence , intent , Silicon Realization , mixed signal , signoff , SoCs

Verification

De-Mystifying SystemC: What is TLM?

In my last post I briefly mentioned that when designing hardware with SystemC, you…

• 2 min read
High-Level Synthesis , Registers , TLM , Models , C to Silicon , transaction level modeling , SystemC , Modeling , System Design and Verification

System, PCB, & Package Design 

Team Allegro Continues Demonstration of New PDN Analysis Technology at DesignCon…

Today at DesignCon, drop by the Cadence booth to see TeamAllegro continue the demonstration…

• 1 min read
PCB SI , PCB , PCB PI , PDN , Power Delivery Network , PCB Signal integrity , IR drop , power , Allegro

System, PCB, & Package Design 

What's Good About Capture Locking Objects? The Secret's in the SPB16.3 Release!

The Allegro Design Entry CIS (Capture - Allegro flow) now includes an object locking…

• 1 min read
SPB16.3 , Design Entry CIS , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , OrCAD , Design Entry , Schematic , Allegro

System, PCB, & Package Design 

Cisco and Cadence Present Co-design Paper at DesignCon

Today at DesignCon, be sure to drop by Room 203 at 11:05 and see Cisco and Cadence…

• 1 min read
SiP , DesignCon , IC Package , Digital SiP design , Cisco , IC Packaging & SiP design , Physical layout and co-design

System, PCB, & Package Design 

Team Allegro Showing New PCB PDN Analysis Technology at DesignCon 2011

Today at DesignCon, drop by the Cadence booth to see TeamAllegro demonstrate the…

• 1 min read
PCB , PCB PI , PDN , PCB Signal and power integrity , Power Delivery Network , full wave , IR drop , power , Allegro

System, PCB, & Package Design 

Team Allegro to Boost Power of PCB PDN Solution – Sneak Peek at DesignCon 2011

The Cadence booth at DesignCon 2011 will provide visitors with a demonstration of…

• 1 min read
PCB , DesignCon , PCB PI , PDN , PCB Signal and power integrity , TeamAllegro , Power Delivery Network , full wave , IR drop , power , Allegro

Verification

What Could Be Simpler than a Request-Acknowledge Handshake?

My last few blog posts have included three corner-case conditions that led to bugs…

• 3 min read
Functional Verification , bugs , corner cases , formal , intent , assertions , simulation

Digital Design

Tackling your Greatest Chip Design Challenges with the Cadence Digital End-to-End…

It hasn't been that long, but do you recall your new year's resolution? Eat healthier…

• 6 min read
ECO , conformal , Low Power , Encounter Test , gigahertz , giga-gate , 3D-IC , 3DIC , encounter digital implementation system , Mixed-Signal , encounter , rtl compiler , Silicon Realization , Digital Implementation , 3D , mixed signal , Digital end-to-end flow
CDNS - Fix Layout Hompage