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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
cdns - all_blogs_categories

Blog - Post List

Latest blogs

RF Engineering

Using The Composite Triple Beat Source to Speed up QPSS Analysis

Say you have a design with 4 input frequencies: 3164M (vco), 1449M (tone0), 1456M…

• 2 min read
RFIC , QPSS Analysis , CTB , Virtuoso Spectre , Spectre RF , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , spectreRF , RF design , harmonic balance , Composite Triple Beat

SoC and IP

The Flash Factor for Consumer Devices: Will NAND Flash and Hard Disk Storage Coexist…

By Steve Leibson for Denali Software If you spend a lot of time reading and…

• 4 min read

Verification

Changing The "F" in RTFM to "Fantastic"

Talk about unsung -- tech writers just don't get the credit they deserve. They sit…

• 1 min read
Tech Pubs , Functional Verification , Incisive , Kit , IES , IES-XL

Analog/Custom Design

Virtuoso Layout Migrate - 614 Enhancements

Hi, I'm Thibault Alix and I have been working with the VLM team for two years. I…

• 1 min read
Layout Migrate , Virtuoso , IC 6.1.4 , VLM , Custim IC Design , SKILL

Verification

AMIQ DVT Maximizes OVM Reuse Via Methodology Compliance

The Open Verification Component (OVC) defined by the official OVM User Guide in the…

• less than a min read
SystemVerilog , uvm , OVM ML , Functional Verification , OVM , OVM SV , Signal Integrity , AMIQ , IES , IES-XL

System, PCB, & Package Design 

What's Good About Allegro Placement Replication / Fine Tuning? - Look to SPB16.3…

Placement replication was introduced in Allegro PCB Editor SPB16.2. At that time…

• 5 min read
SPB 16.2 , Placement Replication , SPB 16.3 , Allegroro , PCB design

SoC and IP

Low Power DDR Options -- From the Trenches

by Marc Greenberg, Director of Technical Marketing, Denali Software Momentum…

• 3 min read

Verification

Back to Work in 2010

It's back to work in 2010. Thanks for all the great feedback in 2009. I plan to continue…

• 2 min read
global warming , System Design and Verification , code offets , linux

Digital Design

Design Signoff Begins In Implementation

As an ex-design engineer now working in EDA, I am often privileged to see advanced…

• 1 min read
dynamic rail analysis , Static timing analysis , SI , Early Rail Analysis , ets , cadence , EDI system , Signoff Analysis , encounter digital implementation system , EPS , Signal Integrity , Cadence Encounter Power System , Digital Implementation , crosstalk , CeltIC , tapeout , design closure , encounter power system , Encounter Timing System , timing convergence , "SoC-Encounter" , blog

Digital Design

Trying to Figure Out Social Media? Ron Ploof Says "Read This First"

Left to Right: Ron Ploof, Bob Dwyer Photo Credit: brillianthue "As a New Media evangelist…

• 6 min read
Facebook Twitter , New Media , EDA , Social Media , Ron Ploof

Verification

Is The Industry Ready For Mainstream Adoption of Higher Abstraction?

I was recently part of an industry wide interview conducted by Clive "Max" Maxfield…

• 1 min read
TLM , System Design and Verification , SystemC

RF Engineering

NPORT S-Parameter Model Enhancements

In MMSIM 7.2, two new parameters have been added to the Spectre nport primitive:…

• 1 min read
Circuit simulation , MMSIM71 , RFIC , Virtuoso Spectre , Spectre RF , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , harmonic balance

Verification

Adam’s Verification Top 10 In '10

I love top 10 lists. Not so much for the drama of the count-down, but for arguments…

• 3 min read
performance , SystemVerilog , Real Value Modeling , OVM ML , Functional Verification , CPF , OVM , OVM e , Incisive , OVM SV , e , Mixed-Signal , Simulation acceleration , SystemC , VHDL , IES , OVM SC

Verification

Android System Verification Part 5

In the previous article I introduced the use of Specman for generating sequences…

• 2 min read
GPS , android , System Design and Verification

System, PCB, & Package Design 

What's Good About Reflection?

What's good about it is that we don't need to reflect occasionally. We can reflect…

• 1 min read
PCB design , reflection , Allegro

Verification

Formalizing Multilanguage Mixology For e Users

Historically it’s been very common for e users to have to mix other programming languages…

• 4 min read
SystemVerilog , Specman , TLM , methodology , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , C , e , multi-language , SystemC , sequences , ESL , Matlab , IES-XL

Verification

Happy Holidays - OVM on The Path to Standardization

I've just heard that the Accellera VIP Technical Subcommittee (TSC) has voted to…

• 1 min read
uvm , methodology , Functional Verification , OVM , Accellera , verification

Verification

Imitation Is The Sincerest Form Of Flattery - We Thank You!

Let me start by sharing some recent blog activity showing competitors doing some…

• 2 min read
System Design and Verification , Incisive , Incisive Software Extensions , C-to-Silicon Compiler , ESL

RF Engineering

Analyzing Distortion With Spectre RF

Greetings, In the previous appends, we looked at using Shooting Newton Periodic Steady…

• 3 min read
Spectre RF , RF design , pss , FFT , Distortion
CDNS - Fix Layout Hompage