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業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Analog/Custom Design

What Your Circuit Doesn't Know, Can Kill It!

Device variation has been a long-standing problem in custom design. Over the years…

• 1 min read
IP , post-extraction , corner , in-design , Virtuoso Analog Design Environment , physical implementation , device variation , IC design

System, PCB, & Package Design 

Improve Design Quality with Adjacent Layer Object Avoidance in the 16.6 Cadence APD…

In this week's discussion, let's take a look at a cornerstone of every good substrate…

• 2 min read
IC Packaging and SiP Design , package , packaging , IC Packaging and SiP , APD , IC Packaging & SiP design , SiP Layout , IC Package Physical layout and co-design

Verification

e Language Editing with Emacs

Specman and e have been around for a while, and some clever people have developed…

• 1 min read
AF , Specman , Incisive Debug Analyzer , e code , xemacs , Funcional Verification , editing , emacs

Whiteboard Wednesdays

Whiteboard Wednesdays - What is VIP?

Today, our continuing Whiteboard Wednesdays video blog series will provide an overview…

• less than a min read
Verification IP , Memory , VIP , EDA , interfaces , SoC design

System, PCB, & Package Design 

What's Good About Allegro/OrCAD/Sigrity Quarterly Incremental Releases (QiRs)? Check…

You’ve no doubt seen announcements (either via customer emails, on the Cadence website…

• 1 min read
PCB , Allegro 16.6 , 16.6 , Support , SPB , Front-end PCB design , OrCAD , Sigrity , Allegro

Verification

Incisive Verification: Top 10 Things I Learned While Browsing Cadence Online Support…

There is always a demand, in most corners of the world today, for learning and troubleshooting…

• 9 min read
IEEE-1801 , LPS , App Note Incisive Simulation , Cadence Online Support , RAK , UVC , UPF , IES

SoC and IP

My Love-Hate Relationship with Mobile World Congress

My friends are jealous. I get an all-expense-paid trip to Barcelona, Spain to see…

• 1 min read
Design IP , MIPI , Mobile World Congress , MWC , Tensilica

Whiteboard Wednesdays

Whiteboard Wednesdays—Imaging, Video, and Embedded Vision

Today, our continuing Whiteboard Wednesdays video blog series will shed some light…

• less than a min read
Design IP , Whiteboard Wednesdays , IP , video , embedded vision , Tensilica , imaging , imaging video

Verification

Cadence and AMD Add New UVM Multi-Language Features

The UVM Multi-Language Open Architecture open-source library was recently updated…

• 2 min read
IEEE 1647 , SystemVerilog , uvm , IEEE 1800 , UVM-ML , VCs , Incisive , e , IEEE 1666 , Accellera , SystemC , Questa , IES-XL

SoC and IP

Latest Developments in Ethernet Standards

Cadence is committed to supplying Ethernet silicon and verification IP to help its…

• 3 min read
Ethernet standards , IEEE 802.3 , Ethernet , Marris , 802.3bj

System, PCB, & Package Design 

What's Good About Allegro PCB Editor CM Analysis Control? 16.6 Has a Few New Enhancements

Beginning with the 16.6 version of Allegro PCB Editor , you can now toggle the Analysis…

• less than a min read
PCB , constraints manager , Cadence Design Systems , Constraint-driven PCB Design flow , data management , constraint databases , Allegro GUI , Allegro 16.6 , cadence , 16.6 , SPB , PCB Editor , Constraint Manager , PCB routing , design , PCB design , Constraints , Grzenia , Allegro PCB Editor , Constraint Driven PCB routing , PCB Capture , Allegro

Verification

Covering Edges (part II)—“Inverse Normal” Distribution

In the previous example , we used the "select edge" to generate edge values for fields…

• less than a min read
AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming

Whiteboard Wednesdays

Whiteboard Wednesdays - Closing the Memory Wall Gap

We're excited to introduce Whiteboard Wednesdays, a new video blog series that will…

• less than a min read
Design IP , 2D Memory , Memory , DDR4 , 3D memory , wide i/o , HMC , HBM , UFS , eMMC , Tensilica , DDR4 3DS

System, PCB, & Package Design 

What's Good About Allegro PCB Editor New Ratsnest Display Option? Check Out 16.6

The 16.6 Allegro PCB Editor release has a ratsnest display option that is designed…

• less than a min read
PCB , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , Routing , 16.6 , PCB Editor , PCB routing , Layout , design , PCB design , Grzenia , Allegro PCB Editor

Verification

ADI Success Verifying SoC Reset Using X-Propagation Technology - Video

Analog Devices Inc. succeeded in both speeding up the simulation and debug productivity…

• 2 min read
x-prop , Low Power , debug , simvision , CPF , x-propagation , Incisive , UPF , MDV , GLS , verification , IES-XL

Analog/Custom Design

Virtuosity: 15 Things I Learned in December 2013 by Browsing Cadence Online Supp…

With this month's title, I'll need to start adding the year, as this marks the one…

• 3 min read
RF Simulation , AMS , Low Power , PCells , ADE , Layout , Virtuoso , Spectre , Analog Design Environment , ADE-XL , PVS , SKILL

System, PCB, & Package Design 

See the Differences Between Your Designs Visually with the Layer Compare Toolset…

Have you ever wondered exactly what has changed between two different versions of…

• 6 min read
IC Packaging , solder mask layer , substrate , SiP Layout , layer compare tools

Verification

Recap of Another Successful Japan C-to-Silicon User Seminar

Back in November, our Japan office hosted a C-to-Silicon Compiler user meeting. They…

• 3 min read
C-to-Silcon , Renesas , Japan user group , high level synthesis , Fujitsu , Casio

Digital Design

Five-Minute Tutorial: Start the New Year with Voltus

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone…

• 2 min read
voltagestorm , vstorm , rail analysis , EPS , vector-based , Voltus , IRdrop , power grid view , Power Analysis , EM , vectorless , five minute tutorial , power , RAKs , power grid library
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