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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

Favorite Features of an IC Package Designer: Wirebonding

This is the fourth in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , package , IC Package , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , SPB , wirebonding , Physical layout and co-design , Kulicke & Soffa

Analog/Custom Design

SKILL for the Skilled: Making Programs Clear and Concise

The SKILL programming language augments Cadence core tool functionality for Virtuoso…

• 3 min read
Team SKILL , programming , analog , Virtuoso , Custom IC Design , SKILL , Allegro

SoC and IP

STT-MRAM -- from Seagate???

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car…

• 2 min read

Digital Design

CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation

I previously wrote about the general session of the 2010 CDNLive! Silicon Valley…

• 2 min read
EDA360 , Silicon Realization , Digital Implementation , CDNLive!

Verification

Using Scoreboards and Virtual Platforms for Software Verification

Today I'm running a guest article written by Henry Von Bank of Posedge Software …

• 4 min read
scoreboards , software verification , virtual platforms , posedge , virtual prototypes , Incisive , ISX , System Verification , linux

System, PCB, & Package Design 

What's Good About Differential Pairs in Allegro Constraint Manager? See For Yourself…

There are a couple new Differential Pair (Diff Pair) capabilities available with…

• 3 min read
PCB , PCB Layout and routing , DDR2 , SPB16.3 , Constraint-driven PCB Design flow , diff pairs , DRC , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , PCB design , differential Pair Swapping , reflection , Allegro PCB Editor , differential pairs , Differential Pair Support , library , Allegro

Verification

Verification Goldmine: 50 User Papers on Formal, Multi-Engine, and Assertion-Based…

With all due respect to our Tech Pubs writers, Solutions Architects, and contributors…

• 8 min read
verifier , DAC , ABV , methodology , CDNLive , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive , SVA , Silicon Realization , PSL , DVcon , AMBA , MDV , IEV , IFV

Verification

CDNLive! Silicon Valley 2010 in the Rear-View Mirror

Well, we all survived another very busy CDNLive! event last week. Since I posted…

• 2 min read
uvm , CDNLive , OVM , EDA360 , MDV , techtorial , verification

Verification

User Views -- Migrating From FPGA-Based Prototyping to Palladium

In recent posting published by John Cooley on Deepchip.com, users compared FPGA-based…

• 1 min read
emulator , deepchip , prototyping , Palladium , Emulation , Cooley , FPGA

RF Engineering

Virtuoso APS Supports RF Analyses in MMSIM 7.2 and MMSIM 10.1

A new multi-threading capability has greatly improved simulation speed for RF Designers…

• less than a min read
RF , APS , MMSIMM , spectreRF , Spectre

System, PCB, & Package Design 

A Shorter, Predictable Design Cycle for Complex PCBs -- Electrical Constraint Sets…

This is the first in a series of blogs focused on how you can make your design cycle…

• 2 min read
PCB Layout and routing , DDR2 , ECSets , Constraint-driven PCB Design flow , Allegro 16.3 , XAUI , "PCB design" , PCB design , Allegro PCB Editor , Predictable PCB design , DDR3 , Allegro

Digital Design

CDNLive! Silicon Valley 2010: What EDA360 Means to Digital Implementation Engine…

CDNLive! Silicon Valley 2010 -- our user's group meeting and more -- kicked off yesterday…

• 4 min read
CDNLive , system realization , EDA360 , Silicon Realization , Digital Implementation , SoC Realization , CDNLive!

Verification

The Increasingly Hazardous World of FPGA Verification

Last week saw the publication of two interesting blog posts regarding the growing…

• 3 min read
uvm , Verification methodology , Functional Verification , Formal Analysis , OVM , FPGA

Verification

CDNLive! -- Israel and the U.S.

The Cadence Design Network provides a great way to learn about the latest design…

• 1 min read
CDNLive , system realization , Emulation , software , Israel , CDNLive! , embedded , System Design and Verification

Verification

Android, Linaro, and 10 Other Useful Embedded Linux Links

The state of Minnesota is unofficially divided into two parts; The Cities and The…

• 1 min read
android , System Design and Verification , linaro , software , linux , Embedded Linux , embedded

Verification

e Templates and e Macros -- An Update for Specman Users

A couple of recent blogs have mentioned the feature of e templates, which was added…

• 2 min read
Specman , Functional Verification , Incisive , e , team specman , macros , AOP , IES-XL

SoC and IP

Apple boots HDD--completely out of the new MacBook Air notebooks. SSD is the only…

Claiming that the move unifies Apple’s product line, Steve Jobs yesterday announced…

• less than a min read

Verification

Team Verify at CDNLive Silicon Valley Next Week – ABV, Formal, Multi-Engine Verification…

At next week's CDNLive! Silicon Valley in San Jose, California, Cadence will cover…

• 1 min read
NextOp , IP , ABV , methodology , Zocalo , CDNLive , Functional Verification , Formal Analysis , formal , EDA360 , Incisive , Silicon Realization , assertion synthesis , IEV , IFV

Verification

A Preview of Verification Sessions at CDNLive! Silicon Valley

As Cadence followers well know, our annual worldwide series of CDNLive! events is…

• 2 min read
uvm , ABV , CDNLive , OVM , MDV , techtorial , verification
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