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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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Blog - Post List
Latest blogs

Digital Design

Innovate Your Way Out of Recession With the New Encounter!

It's official! The U.S. economy has been in a recession for the past year. …

• 2 min read
Static timing analysis , Early Rail Analysis , SoC-Encounter , Digital Implementation forums , First Encounter , SoC-Encounter 8.1 , Signoff Analysis , STA , encounter , Cadence Encounter Power System , Digital Implementation , CeltIC NDC , Global Timing Debug , Encounter Timing System , SSTA , Floorplanning and Prototyping , "SoC-Encounter"

Verification

News From the IP '08 Conference

My colleagues on the Verification IP team have been honored to present at the annual…

• 3 min read
HW/SW , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , VIP , Coverage-Driven Verification , Multi-domain verification: HW/SW co-verification , ISX (Incisive Software Extensions) , Verification IP modeling , ISX

Digital Design

Demo: Using the Pin Editor in SoC-Encounter

SoC-Encounter has automatic partition pin assignment capabilites. The tool also…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , Digital Implementation , Pin Editor

Verification

Follow-up on Posedge Software Interview

Just a quick follow-up to my previous interview with Henry Von Bank of Posedge Software…

• less than a min read
posedge , System Design and Verification , ISX

Verification

e Running Inside VCS Anniversary Updates?

It's been a year since I heard the first solid report about Synopsys supporting…

• less than a min read
IEEE 1647 , Specman , Testbench simulation , e , multi-language , Incisive Enterprise Simulator (IES) , IES

Digital Design

Tapeout!

With an early December tapeout looming, I've found myself too busy to write a post…

• 3 min read
ECO , LEC , DRC , LVS , Digital Implementation , Power Analysis , tapeout

System, PCB, & Package Design 

What's Good About Advanced Plating Bar Checks - Check out the SPB16.2 Release and…

New functionality has been added to the SPB16.2 Allegro Advanced Package Designer…

• 7 min read
SPB 16.2 , BGA , advanced package designer , advanced plating bar check , PCB design , Allegro

Verification

Virtualization and Verification With Posedge Software

Posedge Software is a Cadence Verification Alliance Member with skills in two of…

• 5 min read
posedge , open virtual platforms , System Design and Verification , OVP , QEMU

Verification

Thoughts on AMS Verification Inspired by the DV Club Lunch

Last week I had the pleasure of attending a DV Club lunch presentation from Dr.…

• 2 min read
AMS , verification strategy , Verification methodology , Functional Verification

System, PCB, & Package Design 

What's Good About HDI Via Structures - Check out the SPB16.2 Release and See!

New functionality has been added to the SPB16.2 Allegro PCB Editor suite of tools…

• 12 min read
SPB 16.2 , LMB , via , PCB design , microvia

Digital Design

Coming This Friday November 14th: SoC-Encounter Office Hours

I've really been enjoying the discussions in our Digital Implementation Forums…

• 1 min read
SoC-Encounter , Digital Implementation forums , chat

Digital Design

How to Change a Net Name

This is a question that comes up once every few months or so: "How do I change the…

• less than a min read
Digital Implementation

Digital Design

Demo: Partitioning a Design in SoC-Encounter

One of the longest standing capabilities in SoC-Encounter is its ability to partition…

• less than a min read
SoC-Encounter , partitioning , hierarchical design , screencast , Digital Implementation

Verification

Heads-up: Formal + Productivity Flow Technical Webinar Coming Up On Nov 12th

Heads-up: there is a free technical webinar next Wednesday 11/12 that goes deeper…

• 2 min read
FPV , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , CDV , Enterprise Manager , Plan and metrics management , coverage driven verification (CDV)

System, PCB, & Package Design 

What's Good About The SPB16.2 Release? WOW - Download It now!

The SPB16.2 release is now available (actually, it was available on 10/31/08 from…

• 2 min read
SPB 16.2 , PCB design , Allegro

Verification

Portable Design Names Cadence Incisive Palladium Dynamic Power Analysis its September…

In his article in Portable Design, John Donovan wrote: Palladium Dynamic Power Analysis…

• less than a min read
Portable Design , System Design and Verification , Palladium

Verification

Welcome Sharath Siddappa From Rambus, You Are The 5000th OVM World Registrant!

Welcome Sharath Siddappa, the 5000th OVM World registrant! In only 10 months, the…

• 1 min read
SystemVerilog , Functional Verification , Open Verification Methodology , Testbench simulation , OVM , eRM , OVMWorld

Verification

OVM - The "O" Means Opportunity

A few months back I blogged that OVM was " Open for Business ". A nice play on words…

• 1 min read
Simantis , eclipse , KPIT , Functional Verification , IBM , Cadence VIP portfolio , OVM , Doulos

Verification

Report From the Advanced Verification Techtorial in San Jose Tuesday 10/28

I'm excited to report that Tuesday's techtorial, covering a range of topics underneath…

• 1 min read
Verification methodology , metric driven verification (MDV) , Functional Verification , Open Verification Methodology , OVM , techtorial
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