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Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
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Blog - Post List
Latest blogs

Breakfast Bytes

Designing for the Cloud

At the recent GSA silicon summit, there was a panel session on designing for the…

• 4 min read
cloud , accelerator , gsa silicon summit , gsa , datacenter

Whiteboard Wednesdays

Whiteboard Wednesdays—Ubiquitous USB Interface Evolution

In this week's Whiteboard Wednesdays video, Arif Kahn details the evolution of the…

• less than a min read
Whiteboard Wednesdays , IP , USB Type-C , USB , Arif Kahn

Breakfast Bytes

Security for IoT Is a Requirement, Not a Choice

It is hard to attend any sort of meeting to do with semiconductors without hearing…

• 4 min read
security , IoT , Internet of Things , gsa , Breakfast Bytes

Verification

Why Do We Need a Verification Language?

This month, we celebrate the 20 th anniversary of Specman’s introduction to the public…

• 4 min read
Specman , e , Aspect Oriented Programming , yoav hollander , verification

Academic Network

What Was on Offer at European Test Symposium (ETS) 2016 in Amsterdam?

IEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting…

• 2 min read
ets , Cadence Academic Network

Academic Network

Students From Tianjin University in China Visit Cadence Sophia

Back in May, Professor Gilles Jacquemod and 9 engineering students from Tianjin University…

• 1 min read
Cadence Academic Network

Breakfast Bytes

Gary Patton: What's Next? Markets and Technology

One of the keynotes at the imec technology forum last month was by Gary Patton, the…

• 3 min read
Automotive , IoT , imec , GlobalFoundries , Breakfast Bytes

SoC and IP

Can You See Me? Putting Neural Networks in Everyday Devices

Neural networks have become very popular today due to their use in leading-edge technology…

• 1 min read
CVPR , Chris Rowen , Computer Vision , Tensilica , neural networks , CNN , image processing

SoC and IP

The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Academic Network

CDNLive EMEA: An Intern's Perspective

CDNLive EMEA is often cited as the most exciting event of the year for Cadence. This…

• 3 min read
Cadence Academic Network , CDNLive EMEA

Breakfast Bytes

99.7% of Transistors Manufactured Are Memory

I was in Brussels a couple of weeks ago to attend imec's annual technology forum…

• 5 min read

Breakfast Bytes

RISC-V—Instruction Sets Want to Be Free

I had never heard of the RISC-V (pronounced five, not vee) instruction set until…

• 5 min read
risc-v , instruction set , krste asanovic , isa , RISC , UC Berkeley , instruction set architecture

Verification

IP Group @ 53rd DAC – Veni Vidi Vici

Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party…

• 2 min read
DAC , Verification IP , IP , DDR4 , LPDDR4 , SerDes

Analog/Custom Design

Waveform Thumbnails

Wouldn't it be great if you could see your plots directly on the schematic? Well…

• 2 min read
Explorer , waveforms , waveform thumbnails

Academic Network

Open Source Raspberry Pi Design Files for Allegro and OrCAD Tools

The Raspberry Pi has firmly established itself as a household name by providing a…

• 2 min read
university , Cadence Academic Network , university program

Breakfast Bytes

Seamless Verification

At DAC, Cadence had their now traditional verification lunch. Brian Fuller returned…

• 6 min read
DAC 2016 , DAC , palladium z1 , virtual platform , Palladium , dac53 , Emulation , FPGA prototyping , simulation , Breakfast Bytes , Formal verification , verification

Academic Network

Cadence Technology Days at MIET

On 21 April, Cadence and the Moscow Institute for Electronics Technologies (MIET…

• 1 min read
MIET , Cadence Academic Network , academic workshop , academia , Russia

Academic Network

Visiting KAUST

Cadence Academic Network is a worldwide activity; therefore, the team members are…

• 2 min read
university , Cadence Academic Network , academic workshop , KAUST

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Fiber Weave Effect—Zig-Zag Routing? New Capabilities…

The 16.6-2015 Allegro PCB Editor release introduces the interactive conversion of…

• 3 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , SPB , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro
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