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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Latest blogs

Breakfast Bytes

Automotive Sensors: Cameras, Lidar, Radar, Thermal

Yesterday I wrote a sort of overview of the Cadence Automotive Summit that took place…

• 9 min read
Automotive , embedded vision , lidar , radar , ISO 26262 , automotive summit

Breakfast Bytes

Breakfast Buffet for November 2018

https://youtu.be/SxGTX1reCVw The three highlighted posts for November were: Diwali…

• less than a min read
breakfast buffet , tpu , google , photonics , PCB design

Digital Design

2018 Annual HLS Survey Results

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey…

• 2 min read
High-Level Synthesis , 5G , survey , machine learning , Stratus , HLS

Breakfast Bytes

Automotive Summit: The Road to an Autonomous Future

Before Thanksgiving, Cadence held an Automotive Summit. I was going to dive into…

• 6 min read
Automotive , functional safety , lidar , radar , camera , ISO 26262

定制IC芯片设计

Virtuoso: 新序曲—针对高频产品设计的Virtuoso RF解决方法

最新发布的Advanced Methodology Virtuoso (ICADVM18.1) 引入了Virtuoso RF 解决方法，用户可以利用新的封装设计功能在Virtuoso…

• less than a min read
Chinese blog , Cadence blogs , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , VRF , Virtuoso Schematic XL , VMT , vsdp , RF design , Custom IC Design , Virtuoso Layout Suite XL

Digital Design

ECO with Stratus HLS and the Digital Implementation Flow

For years chip designers have dealt with ECO’s when their source code was written…

• 4 min read
High-Level Synthesis , ECO , Conformal ECO Designer , Stratus , HLS

Breakfast Bytes

The Conway Disappearance Effect

Over Thanksgiving weekend, Lynn Conway sent me a link to an article that she'd written…

• 9 min read
mead and conway , lynn conway

Breakfast Bytes

IEDM: All About Interconnect

The first week of December means it is IEDM, the International Electron Devices Meeting…

• 11 min read
IBM , Samsung , transistor , cfaed , tuv dresden , IEDM

定制IC芯片设计

Virtuoso: 新序曲-Simulation Driven Routing 工具简介

总结（摘要）：新版的Virtuoso平台（*ICADVM18.1）提供了突破性的分析功能和创新性的仿真交互布线，用于更为更为强大，更为高效的设计，同时也为最先进的工艺技术提供了强有力的支持…

• less than a min read
Interactive Routing , EAD , Chinese blog , Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , electrically aware design , Virtuoso Advanced Release , Simulation-driven interactive routing , Layout , Virtuoso , mixed signal , Custom IC Design , Custom IC

Breakfast Bytes

RISC-V: Real Products in Volume

I titled my preview of the RISC-V Summit RISC-V Summit Preview: Pascal or Linux?…

• 6 min read
Western Digital , risc-v , NXP , fadu , vega , Qualcomm , sifive

Breakfast Bytes

Sunday Brunch Video for 9th December 2018

https://youtu.be/M_d-K4yE_n4 Made on Cadence pathways (camera Sean) Monday: ICCAD…

• less than a min read

PCB、IC封装：设计与仿真分析

针对电气工程师的热管理基础——第四篇

作者：Lawrence Der 在热管理基础知识的 第一篇 中，我们讨论了电域和热域之间的二元性。 第二篇 中，我们研究了三种不同的热传输机制，并将它们与等效热阻相关联…

• less than a min read
PCB , 热 , Chinese blog , 热分析 , 温度 , 中文 , Sigrity , PowerDC , 传热 , 热基础

Breakfast Bytes

The Mother of All Demos

It is the 50th Anniversary on Sunday of a demo that took place on December 9th 1968…

• 5 min read
stanford research institute , doug engelbart , SRI , mother of all demos

Analog/Custom Design

Virtuosity: Designing a Row-Based Layout Methodology – Why does this Make Sense at…

At advanced nodes, the complexity and volume of design rules have been growing exponentially…

• 5 min read
ICADVM18.1 , Advanced Node , Virtuoso Placer , Virtuoso , Virtuosity , Custom IC Design , Virtuoso Layout Suite , Row-Based Placement

The India Circuit

One Cadence, One Team, One...

One Cadence, One Team, aaaanddd... One Family! This time of year sees all the India…

• 1 min read
GPTW , Family Day , Cadence India

Breakfast Bytes

Semiconductor 2018: Up and to the Right...But Memory Way Up

I was at a meeting of the ESD Alliance (probably still called EDAC back then) when…

• 5 min read
Intel , Memory , Micron , NVIDIA , SanDisk , Samsung , EDA , broadcom , Toshiba , ic insights , Semiconductor , Qualcomm , SK Hynix

Breakfast Bytes

Benedict's Christmas Present...ation: The End of the Beginning

Every year Benedict Evans of a16z does a "big" presentation on the future of mobile…

• 8 min read
benedict evans , Internet , a16z

Breakfast Bytes

Clayton Christensen on the Prosperity Paradox

Probably my favorite business book ever is Clayton Christensen's The Innovator's…

• 12 min read
clayton christensen , prosperity paradox , innovator's dilemma

Breakfast Bytes

ICCAD and Open-Source CAD

Every year in November it is ICCAD, officially the International Conference on Computer…

• 5 min read
woset , ICCAD , open source
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