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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

HOT CHIPS: The AWS Nitro Project

In 2016, Amazon acquired the Israeli company Annapurna Labs. Since they were in stealth…

• 6 min read
ec2 , nitro , cloud , annapurna , aws , Amazon

Whiteboard Wednesdays

Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA…

In this week's Whiteboard Wednesdays video, Tom Hackett continues his introduction…

• less than a min read
Whiteboard Wednesdays , FEM , Electromagnetic analysis , finite element analysis , Clarity 3D Solver , FEA

System, PCB, & Package Design 

IC Packagers: Wrap Your Hands Around a Coil

Coils are a design element that, if not exceedingly common, are showing up in more…

• 2 min read
SiP Layout

Breakfast Bytes

The 2019 Kaufman Award Goes to Mary Jane Irwin

This year's Kaufman Award recipient is Dr. Mary Jane (Janie) Irwin of Pennsylvania…

• 3 min read
Kaufman Award

Breakfast Bytes

TSMC OIP: Process Status

Last week was TSMC's Open Innovation Platform Innovation Forum (aka OIP). Dave Keller…

• 7 min read
OIP , TSMC

Breakfast Bytes

Sunday Brunch Video for 29th September 2019

https://youtu.be/zU_y5sQBlGA Made at TSMC OIP Symposium (camera Tom Hackett) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: PCB Electronics - Three Routing Challenges and Their Solutions

Routing is the core of a PCB. And, it's not an easy task. There are many challenges…

• 4 min read
PCB Layout and routing , PCB Editor

Analog/Custom Design

Virtuosity: Automated Device Placement and Routing—WSP-Based Tree Style Device R…

This blog provides an overview of the last step of the Virtuoso Automated Device…

• 4 min read
automatic routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , EXL , Automated Device-Level Placement and Routing , Automatic Placement , Virtuoso Placer , Layout EXL , Auto P&R , Virtuoso Placement , Placement , tree router , Custom IC Design

PCB、IC封装：设计与仿真分析

Ken的博客系列之八 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：反向信道训练 自动合规性检查 有了详细的布局后互连以及IBIS-AMI模型的正确执行，您可以关注特定的、感兴趣的接口（本例中为PCI…

• less than a min read
SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性 , SI分析与建模

Breakfast Bytes

Building Neural Networks with High-Level Synthesis

Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus…

• 4 min read
deep learning , TensorFlow , Stratus , high level synthesis , HLS

Breakfast Bytes

TSMC OIP: 6nm and 5nm

Today it is TSMC's Open Innovation Platform Ecosystem Forum, or OIP for short. This…

• 1 min read
OIP , n5 , n5p , TSMC , photonics , n7 , n6

Breakfast Bytes

Embedded Development: Specialized Processing

Yesterday, in Running the Program for an Embedded System , I wrote about using emulation…

• 6 min read
domain specific computing , caffe , TensorFlow , Green Hills , C++ , Matlab

Whiteboard Wednesdays

Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA…

In this week's Whiteboard Wednesdays video, Tom Hackett begins a 2-part introduction…

• less than a min read
celsius , Whiteboard Wednesdays , FEM , Computational Fluid Dynamics , Thermal Analysis , finite element analysis , FEA

Breakfast Bytes

Running the Software for an Embedded System

A big challenge with developing a modern SoC is developing the software. Not so much…

• 6 min read
virtual platform , Palladium , embedded software , Emulation , protium s2 , software development

System, PCB, & Package Design 

IC Packagers: Finding Design Issues in SiP - Three Options for DRC Management During…

Your design is complete. Yet, you have 20 DRC violations that need to be addressed…

• 5 min read
APD , SiP Layout

Analog/Custom Design

Virtuoso Meets Maxwell: Help With Electromagnetic Analysis—Part I

This blog is the first one in the multi-part series that aims at providing some in…

• 5 min read
ICADVM18.1 , Virtuoso Advanced Release , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Electromagnetic analysis , Custom IC Design , Virtuoso Layout Suite , Custom IC

Breakfast Bytes

CDNLive Israel 2019: Celsius, the Dead Sea, Ramallah

The big announcement at CDNLive Israel was during Anirudh's keynote when he announced…

• 5 min read
palestine , CDNLive , cdnlive israel

Breakfast Bytes

Sunday Brunch Video for 22nd September 2019

https://youtu.be/6p94sN1fHFY Made at Tel Aviv seafront (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Breakfast Bytes

500th Anniversary of Magellan's Voyage

Earlier this year, on July 20, we celebrated the 50th anniversary of the first landing…

• 5 min read
exploration , Apollo , magellan
CDNS - Fix Layout Hompage