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Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Breakfast Bytes

Jobs: Farmer

Last summer, I took Fridays to write about technology museums. I planned to do a…

• 7 min read
farmer , jobs

Verification

Is Ethernet Ready for the Automotive Market?

Consumer demand for advanced driver assistance and infotainment features are on the…

• 1 min read
Verification IP , VIP , Ethernet standards , Automotive Ethernet , IEEE 802.3 , Ethernet , TSN , Ethernet PHYs

Breakfast Bytes

The Brief but Spectacular History of Shockley Labs

If you read my post Who Put the Silicon in Silicon Valley? then you know my conclusion…

• 9 min read
Stanford , shockley , fairchildren , Fairchild

Verification

Integration and Verification of PCIe Gen4 Root Complex IP into an Arm-Based Server…

Learn about the challenges and solutions for integrating and verification PCIe(r…

• less than a min read

Breakfast Bytes

SEMICON 5nm: 7nm Is Just a Dress-Rehearsal

Usually I don't go to the last day of SEMICON West since not much happens that day…

• 5 min read
asml , 5nm , stochastics , GlobalFoundries , 7nm , EUV

Breakfast Bytes

What's For Breakfast? Video Preview August 20th to 24th 2018

https://youtu.be/6a0znbVfFJk \ Coming from the Cadence parking lot (camera Sean…

• less than a min read
management , jobs

Breakfast Bytes

CDNDrive Automotive Solutions: the Rear Wheels

Yesterday was the first of two posts about Cadence Automotive Solutions. Today we…

• 4 min read
Automotive , legato , functional safety , ISO 26262 , reliability

The India Circuit

6 Reasons To Register for CDNLive India Today!

CDNLive India 2018 is just around the corner! In a few weeks’ time, on the 6th and…

• 2 min read
CDNLive India , CDNLive , broadcom , Texas Instruments

Analog/Custom Design

Virtuoso: The Next Overture – Introducing Design Intent

Simplifies the defining of design goals and gives layout designers the freedom to…

• 4 min read
Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso Design Intent , Virtuoso Schematic XL , Virtuoso , Layout design , Constraints , Custom IC Design , Custom IC , Schematic , Virtuoso Layout Suite XL

Breakfast Bytes

CDNDrive Automotive Solutions: the Front Wheels

Harold Wilson, then Britain's Prime-minister, once said, "A week is a long time in…

• 4 min read
Automotive , legato , functional safety , Tensilica , ISO 26262 , FITS

Breakfast Bytes

The Birthplace of Silicon Valley: 391 South San Antonio Road

The birthplace of Silicon Valley really does have an address, 391 South San Antonio…

• 4 min read
fairchild semiconductor , computer history museum , shockley laboratory

Breakfast Bytes

Deep Learning and the Cloud

It is an exaggeration to say that deep learning requires the cloud, but the standard…

• 6 min read
summit supercomputer , magestic , cadence cloud

Breakfast Bytes

What's For Breakfast? Video Preview August 13th to 17th 2018

https://youtu.be/H03oGGaUfQo Coming from Stevens Creek Mini (camera Sean) Monday…

• less than a min read
Automotive , shockley , cloud , Fairchild , 5nm , 7nm , EUV

Breakfast Bytes

Breakfast Buffet for July

https://youtu.be/JQz3cseZcZc The three highlighted posts for July were: CDNLive…

• less than a min read

System, PCB, & Package Design 

EE Thermal 101 – Thermal Basics for Electrical Engineers (Part 3 of 4)

In part 2 of this blog series we looked at the three different modes of heat transfer…

• 8 min read
EE Thermal , temperature , Thermal Basics , Heat transfer , PowerDC

Breakfast Bytes

CHIPs in the Cadence Cafeteria

Last week it was the Annual San Jose Intern Showcase, in which the San Jose based…

• 4 min read
Interns , intern showcase , chips

PCB、IC封装：设计与仿真分析

升级到Allegro17.2-2016的10大理由

Cadence Allegro 17.2-2016是过去十年中发布的最大版本，于2016年4月下旬发布。由于17.2-2016版本包含数据库更改，通常会出现在零版本中…

• 1 min read
PCB , Chinese blog , Allegro 17.2 , 升级 , Allegro GUI , 约束管理器 , 布线 , 约束驱动的PCB设计流程 , PCB设计 , 中文 , OrCAD , Sigrity , Allegro PCB Editor , 刚柔结合 , Allegro

Breakfast Bytes

CDNLive Japan: The Fourth Industrial Revolution and the Third Dimension

At CDNLive Japan, Tom Beckley gave the keynote Enabling the Fourth Industrial Revolution…

• 8 min read
cdnlive japan , Tom Beckley , Power Integrity , 4th industrial revolution , Signal Integrity , Thermal Analysis , Sigrity

Analog/Custom Design

Virtuoso: The Next Overture – DRD Launches New Interface

If you’ve been anywhere near the Cadence news buzz the last couple of months, you…

• 3 min read
Virtuoso Next , Virtuoso Overture , Virtuoso New Design Platform , Virtuoso Advanced Release , Virtuoso , DRD , New in EDA , Custom IC Design , Custom IC
CDNS - Fix Layout Hompage