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Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured
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System, PCB, & Package Design 

Power Issues? Manage Your IR Drop The "Advanced" Way

Just added to the Cadence Resource Library for Allegro PCB SI is a whitepaper written…

• less than a min read
16.01 , PCB Layout and routing , SPB 16.2 , PCB Signal and power integrity , Allegro 16.2 , SPB16.2 , PCB design

Verification

A Quick Look Back at DAC

Well, I had good intentions of blogging from DAC , or at least summarizing my four…

• 1 min read
DAC , Verification methodology , Functional Verification , Open Verification Methodology , OVM

Analog/Custom Design

We Interrupt Your Regularly Scheduled Programming...

I thought I would have time for a regular TYDKAV (Things You Didn't Know About Virtuoso…

• 1 min read
ViVa-XL , IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , Custom IC Design

Verification

A Classification of ESL - High Level Synthesis Tools

These days, there is a lot of talk of what the next design methodology for Digital…

• 3 min read
RTL , System C , ESL , System Design and Verification

Verification

Full System vs Sub-system Virtual Prototyping

There is a strong movement in the industry to move to create Virtual Prototypes of…

• 2 min read
TLM , RTL , System Design and Verification , virtual prototype

SoC and IP

Reflections on Life and Death in the Memory Sector: Spansion and Qimonda, Long on…

Hammered by market events, two significant memory suppliers suffer in Chapter 11…

• 6 min read

Verification

Intel vs ARM - Did the Embedded Systems Conference India Shed Light on the Battle…

Being a Brit, Cricket is never very far from my thoughts especially when travelling…

• 2 min read
Intel , Low Power , System Design and Verification , embedded software , ARM

Digital Design

5 Fascinating People I Met at the 2009 Design Automation Conference

As much as the Design Automation Conference (DAC) is about demonstrating solution…

• 5 min read
DAC , Digital Implementation

Verification

Post-DAC 2009 Survey on The XJTAG Girls

One non-technology item that received an extraordinary buzz at DAC 2009 were the…

• 1 min read
DAC , Functional Verification

Verification

1st Ever Virtual Platform Workshop Deemed a Success

Yesterday DAC hosted the first ever Virtual Platform Workshop , a full day dedicated…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification

System, PCB, & Package Design 

What's Good About Cavity Support in APD? You'll see for yourself using the SPB16…

No - we're not talking teeth, candy, and cavities here ... Many customers have been…

• 3 min read
SPB 16.2 , APD , PCB design

Verification

Finding the Opportunities in ESL

I came to DAC 2009 looking for the industry trends in ESL, because as we all know…

• 2 min read
DAC 2009 , virtual platform , System Design and Verification , ESL High Level Synthesis

Verification

Day 1 of DAC is a Wrap

Well, it was a half day at DAC for me as I suffered a 2 hour flight delay from Minneapolis…

• 3 min read
DAC , TLM 2.0 , System C , OSCiI , System Design and Verification

Analog/Custom Design

Things You Didn't Know About Virtuoso: Customizing the Library Manager

I've told you in previous postings about some new features in Virtuoso IC6.1 which…

• 3 min read
IC 6.1 , Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Customer Questions About TLM-driven Design and Verification

In the latest blog published by Ron Wilson there were two questions about our TLM…

• 1 min read
System Design and Verification , TLM 2.0 , System C , C-to-Silicon , high level synthesis

Verification

DAC 2009 News: Specman 9.2 Highlights + Beta Program Invitation

Specmaniacs, With the start of DAC 2009, Team Specman is excited to finally be able…

• 1 min read
DAC , IntelliGen , Specman , Functional Verification , simvision , OVM e , e , SystemC , IES-XL

SoC and IP

Rethinking SSDs?

NAND Flash's SSD Vision: Wholesale replacement of HDDs by SSDs in the huge market…

• 7 min read

Verification

FSM Mnemonics Maps (Enums) in SimVision Using Verilog 1364

The mighty FSM – you first learned it when you were a young pup at University (some…

• 1 min read
SystemVerilog , debug , Functional Verification , simvision , Verilog , IES

Digital Design

Reducing Risk and Improving Productivity with the Cadence InCyte Chip Estimator and…

I'm looking forward to heading out to San Francisco next week for the 46th Design…

• 1 min read
DAC , Digital Implementation , Cadence InCyte Chip Estimator , Encounter Digital Implementation System 8.1
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