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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

X-FAB's Innovative Communication and Automotive Designs: Powered by Cadence EMX Planar…

Using the EMX solver, X-FAB design engineers can efficiently develop next-generation…

• 1 min read
EM Analysis , electromagnetics , in-design analysis , reference design , Electromagnetic analysis , PDK , foundry

Breakfast Bytes

Sunday Brunch Video for 31st July 2022

https://youtu.be/bym7Az0BZdY Made in my Mini Monday: Cadence Expands into Molecular…

• less than a min read
sunday brunch

Analog/Custom Design

Virtuosity: Custom IC Design Flow/Methodology - Circuit Physical Verification & Parasitic…

Read this blog for an overview to the Circuit physical verification and parasitic…

• 6 min read
design rule violations , Extraction , Layout versus schematic , Physical Verification System (PVS) , Virtuoso , Quantus Extraction Solution , PVS , Custom IC Design , parasitics

Breakfast Bytes

July Update: ST, GF, Arm, GPUs...and just CHIPS

Finally, a monthly update which appears in its advertised slot on the last Friday…

• 4 min read
GPU , mclaren , ST Microelectronics , GlobalFoundries , ARM , chips act

Analog/Custom Design

Start Your Engines: An Innovative and Efficient Approach to Debug Interface Elements…

This blog introduces you to an efficient way to debug interface elements or connect…

• 4 min read
connect modules , mixed signal design , featured , interface elements , AMS Designer , mixed-signal simulation , Virtuoso , SimVision-MS

Breakfast Bytes

AEK: Powerpoint Is Easy—Change is Hard

I wrote my first post about Automobil Elektronik Kongress 2022 earlier this week…

• 7 min read
Automotive , aek , ludwigsburg , automobil elektronik kongress

System, PCB, & Package Design 

SI/PI Simulation and Measurement Correlation Forum

Join this insightful on-demand webinar event "SI/PI Simulation and Measurement Correlation…

• 1 min read
electromagnetics , Power Integrity , in-design analysis , Signal Integrity

Breakfast Bytes

AEK: Semiconductors: The Base for the Software-Defined Car

At this year's Automobil Elektronik Kongress, there was a panel session titled Semiconductors…

• 10 min read
risc-v , NXP , mercedes-benz , ARM , automobil elektronik kongress

Computational Fluid Dynamics

Seakeeping Observations of SA Agulhas II Using Cadence Fidelity FINE/Marine

The shift left approach is slowly being realized and employed in the marine industry…

• 3 min read
CFD , Marine Engineering , C-Wizard , Pointwise , Fidelity CFD , engineering , simulation software , NUMECA , Meshing , Ships , seakeeping

Breakfast Bytes

Automobil Elektronik Kongress 2022

For me, the must-attend event to understand what is going on in the automobile industry…

• 5 min read
Automotive , automobile elektronik kongress , aek , ludwigsburg

Verification

Stay Ahead of Competition with Real-Time Cross-Team Collaborations

To stay ahead in competition in chip design real-time collaborations ensure traceability…

• 4 min read
collaboration , Palladium , verification management , Traceability , vManager

Life at Cadence

What’s Driving the Automotive Industry in 2022?

Cars are becoming computers on wheels with more processing power than the average…

• 6 min read
Automotive

Breakfast Bytes

Cadence Expands into Molecular Simulation with Acquisition of OpenEye Scientific

This morning, Cadence announced that it has entered into a definitive agreement to…

• 3 min read
openeye scientific , openeye , orion , molecular simulation

Analog/Custom Design

Spectre Tech Tips: Introducing Spectre X EMIR Voltus-XFi

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides…

• 3 min read
Spectre X EMIR , Voltus-Fi-XL , Virtuoso Analog Design Environment , Spectre X distributed simulation , Spectre X Simulator

Breakfast Bytes

CadenceLIVE: Pegasus on AWS, Let Physical Verification Fly

At CadenceLIVE Silicon Valley, Ahmed Elzeftawi of AWS and Dibyendu Goswami of Cadence…

• 4 min read
Physical verification , pegasus , DRC , cloud , aws , cadence cloud

Academic Network

Cadence Academic Network at 59DAC

The Cadence Academic Network was excited to participate in many activities at the…

• 2 min read
DAC , Young Fellows , featured , Cadence Academic Network , CMC Microsystems

System, PCB, & Package Design 

In-Design Analysis in the Cloud with Cadence OnCloud

Last month at CadenceLive Silicon Valley, Cadence introduced a software-as-a-service…

• less than a min read
Power Integrity , in-design analysis , Signal Integrity , electromagnetic , thermal

Breakfast Bytes

ITF USA: Luc Van den hove on Deep Tech

The afternoon of the Monday of SEMICON West is always the Imec Technology Forum …

• 6 min read
itf usa 2022 , imec , itf

System, PCB, & Package Design 

System Analysis Knowledge Bytes: Accelerating Early Stage Design Sign-Off Using PCIe…

This blog talks about how the Cadence®︎ AdvancedSI tools, which are packaged in the…

• 4 min read
Sigrity and Systems Analysis , High Speed Structure Optimization , PCIe , Signal Integrity , High Speed design , power-aware SI
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