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Cadence Japan

【ホンダHGR＋ケイデンス前編】Physical AIの“Physical”とは何か─現実に勝てないAIは、動けない

※本記事は、Honda総合研究センター/HGRに掲載された記事を、同社の許諾を得て転載しています。 皆さん、こんにちは。HGRセンター長の小川厚（おがわ あつし…

Cadence Japan
• less than a min read
featured , japanese blog

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Breakfast Bytes

TSMC Technology Symposium 28...22...16...12...7...

This is the second of two posts about last week's TSMC Technology Symposium. The…

• 7 min read
OIP , n5 , 12FFC , TSMC , TSMC Technology Symposium , n7+ , n7

Whiteboard Wednesdays

Whiteboard Wednesdays - Introduction to Convolutional Neural Networks (CNN)

In this week's Whiteboard Wednesdays video, the first in a two-part series, Megha…

• less than a min read
Automotive , deep learning , vision , convolutional neural networks , mobile , ADAS , CNN

Breakfast Bytes

What's For Breakfast? Video Preview March 27th to 31st 2017

https://youtu.be/-_33atq9vRY Coming from National Automobile Museum, Reno,…

• less than a min read
ESDA , circle of life , lanza techventures , Lucio Lanza , system design enablement , SDA , esd alliance , virtual dummy metal fill

Breakfast Bytes

TSMC Technology Roadmaps

TSMC had their annual Technology Symposium last week. As always, my post comes with…

• 6 min read
Automotive , n5 , IoT , TSMC , HPC , n7 , mobile , n10

Academic Network

The Worldwide MEMS Design Contest Officially Starts

Cadence, X-FAB, Coventor and Reutlingen University have Selected 10 Design Teams…

• 2 min read
Cadence Academic Network , X-FAB , MEMS Design Contest , Reutlingen University , CDNLive EMEA , Mixed-Signal , Coventor

Breakfast Bytes

CDNLive Silicon Valley Preview

Yes, it's that time of year again. Just like a cat has nine lives, Cadence has nine…

• 2 min read
microsoft , CDNLive , Santa Clara Convention Center , CDNLive Silicon Valley

Breakfast Bytes

Dracula, Vampire, Assura, PVS: A Brief History

Cadence was created from the merger of SDA and ECAD, as you probably know. SDA had…

• 9 min read
Extraction , Dracula , DRC , vampire , design rule check , Assura

Breakfast Bytes

Andy Bechtolsheim Keynote on the Future of Networking

At the recent Linley Cloud Hardware Conference, the keynote was given by Andy Bechtolsheim…

• 7 min read
andy bechtolsheim , arista networks , andreas bechtolsheim , linley cloud hardware conference , Linley

Breakfast Bytes

TSMC Announces New 12FFC Process

Today at the TSMC Technology Symposium, Cliff Hou, TSMC's VP of R&D, is set to announce…

• 4 min read
Design IP , 12FFC , TSMC , TSMC Technology Symposium , 12nm , InFO , 7nm

Breakfast Bytes

What's For Breakfast? Video Preview March 20th to 24th 2017

https://youtu.be/Qm8epP4YobA Coming from TSMC Technology Symposium, Santa Clara…

• less than a min read
Léman Micro Devices , CDNLive , SDE , 12FFC , TSMC , TSMC Technology Symposium , InFO , mobile , blood pressure , system design enablement , 7nm , Smartphone

Analog/Custom Design

Virtuoso Video Diary: Real-Time Tuning—A Lot More Than Just an Assistant!

Have you ever found yourself in situations where you’re not sure which values of…

• 3 min read
Analog Design Environment , ADE Explorer , Analog Simulation , analog , Mixed-Signal , Virtuoso Analog Design Environment , Analog Design Environment , ViVA , Virtuoso Video Diary , Custom IC Design

Whiteboard Wednesdays

Whiteboard Wednesdays - Display Stream Compression: Higher Display Resolutions in…

In this week's Whiteboard Wednesdays video, Alex Passi takes a closer look at Display…

• less than a min read
mobile devices , Whiteboard Wednesdays , MIPI , MIPI protocols

Breakfast Bytes

Cadence at MWC: Does This Headset Make Me Look Silly?

Cadence has attended MWC ever since it acquired Tensilica, and they attended for…

• 4 min read

Digital Design

Have DRC Tools Run Out of Steam? – Part 1

In the EDA history of design rule check (DRC), there have been two distinct eras…

• 3 min read
Physical verification , DRC , design rule check

Breakfast Bytes

ESD Alliance Panel on Energy Policy for the IoT Era

BREAKING NEWS: I just received an email that the panel I wrote about here has been…

• 4 min read
california energy commission , energy policy , ESDA , IoT , Internet of Things , san jose city hall , cec , esd alliance

Verification

Static Members in e

How do you define elegant or clean code? Usually, you know it when you see it; defining…

• 9 min read
Specman , Incisive , e language , static , xcelium , verification

Breakfast Bytes

Reliability in Monterey: a Preview of IRPS

The major conference on semiconductor reliability is the International Reliability…

• 4 min read
international reliability and physics symposium , Intel , IBM , Monterey , irps , NASA , reliability

Breakfast Bytes

GF Silicon Photonics: Fiber Attach Is the Secret Sauce

A lot of constraints in datacenters are fixed even though others are increasing.…

• 5 min read
fiber attach , linley group , linley cloud hardware conference , silicon photonics , GlobalFoundries

Analog/Custom Design

Virtuoso Video Diary: Noise Simulation in Spectre RF Using Improved Pnoise/Hbnoise…

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM…

• 4 min read
Spectre RF , noise simulation , Virtuoso , Virtuoso Video Diary
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