Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Cadence Japan

プネー拠点設立20周年を迎えるケイデンス、長期的な研究開発へのコミットメントを強化

ケイデンスのプネー拠点は設立20周年。DSP IPやAIアクセラレータなど最先端の半導体IPを開発し、インドの人材育成・半導体戦略を推進。

Cadence Japan
• less than a min read
news story , featured , Cadence Culture , japanese blog

Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

SoC and IP

Enterprise-class HDDs due to disappear, soon. All hail the enterprise-class SSD.

The great Grand Poobah of SSD research Jim Handy released an industry report on Enterprise…

• 1 min read

SoC and IP

Last call for free DAC tix

The DAC 2010 (DAC47) free exhibit passes program has been a big success with more…

• 1 min read

Verification

Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications…

• 5 min read
Specman , TLM , OVM ML , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , CtoSilocon , OVM SV , e , Enterprise Manager , Palladium XP , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , IES-XL

Verification

FMCAD Call for Papers Extended to May 12

Team Verify would like to inform you about the final call for papers for FMCAD 2010…

• 7 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

SoC and IP

SSDs don’t need disk interfaces. Case in point: OCZ’s USB 3.0 SuperSpeed Enyo

Most SSDs are designed to be interface- and form-factor-compatible with existing…

• 1 min read

SoC and IP

New White Paper discusses the challenges of chip design based on AMBA 4

ARM’s series of AMBA specifications have become a de facto standard for SoC (system…

• 2 min read

SoC and IP

Memory Market Outlook for 2010: How Bad (or Good) is it?

If you’ve been following the roller-coaster ride that constitutes the global semiconductor…

• less than a min read

System, PCB, & Package Design 

What's Good About DEHDL Alignment? You’ve got it in the SPB16.3 Release!

Schematic construction requires a lot of effort in placing components, wires and…

• 2 min read
Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Component Alignment , SPB , Design Entry HDL , Front-end PCB design , Design Entry , ConceptHDL , Schematic

Verification

Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN…

• 3 min read
SystemVerilog , when sub-typing , tweeting , Specman , Functional Verification , when inheritance , OVM , OVM e , OVM SV , e , Twitter , AOP , IES-XL

Verification

What Does EDA360 Mean for Verification Engineers?

I trust that most of you have seen the recent flurry of blog posts and articles about…

• 2 min read
uvm , IP , Verification methodology , OVM , VIP , EDA360

Verification

System Realization activities at CDNLive! EMEA this week

CDNLive! EMEA will be held in Munich again this year, and there’s lots of news about…

• 2 min read
System Design and Verification , cdnLive! system realization

SoC and IP

Magnetic nanodot materials breakthrough presages high-density MRAM--possible competition…

From North Carolina State University (NCSU) comes news of a materials breakthrough…

• 1 min read

SoC and IP

More free DAC exhibit tix; One more chance to win an Apple iPad

A bit more than a week ago, this blog carried the news that you could get a free…

• 1 min read

SoC and IP

Samsung announces imminent release of a multichip module integrating DRAM and PCM…

Hot on the heels of Numonyx’ announcement of two commercial PCM (phase-change memory…

• 1 min read

Verification

See You at CDNLive! EMEA

Today, Team Specman reported that next week's CDNLive! is shaping up to be a big…

• 2 min read
CDNLive!ive! , System Design and Verification

Verification

2010 CDNLive Munich Guide for Specmaniacs

Good news for Specmaniacs based in the EU: next week from May 4-6 is the annual CDNLive…

• 2 min read
Specman , CDNLive , Functional Verification , Cadence VIP portfolio , OVM , OVM e , e , Mike Stellfox , techtorial

Verification

Team Verify's 2010 CDNLive Munich Guide

We're excited to report that next week's annual CDNLive! event in Munich will feature…

• 1 min read
ABV , CDNLive , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , Contributions , SVA , PSL , MDV , IEV , IFV

System, PCB, & Package Design 

What's Good About APD’s Super Smooth Routing? See for yourself in the SPB16.3 Release

When using the point-to-point routing in the packaging products ( APD and SIP ),…

• 3 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , IC Packaging , Allegro 16.3 , SPB 16.3 , APD , advanced package designer , PCB design , Allegro PCB Editor , Cline change

Verification

Harris-Cadence-Mathworks-Xilinx Success Cuts Verification Time 85%

More and more often it takes a village to achieve verification success. As reported…

• 1 min read
Functional Verification , Incisive , xilinx , IES , FPGA , Matlab , IES-XL
CDNS - Fix Layout Hompage