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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Knowledge Booster Training Bytes – Interactive Short Locator (ISL) in the PVS LVS…

Check out this blog to see how you can debug shorts using Interactive Shorts Locator…

• 4 min read
Cadence Digital Badges , Cadence Blended Training , Physical Verification System (PVS) , Cadence training , training bytes , Cadence certified , Virtuoso Video Diary , Cadence Education Services , PVS , ISL , Custom IC Design

Analog/Custom Design

Virtuosity: Custom IC Design Flow/Methodology – Circuit Layout

Read this blog for an overview to the Circuit Layout design stage in Custom IC Design…

• 6 min read
Virtuoso Schematic Editor , Virtuoso Space-based Router , Virtuoso Placer , Layout Suite , Layout , ICADVM20.1 , Custom IC Design , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , IC6.1.8 , Virtuoso Layout Suite XL

Breakfast Bytes

Photonics Keynote: Transitioning from Electrical to Optical I/O

At last year's Photonics Summit, actually held earlier this year due to technical…

• 5 min read
Intel , Photonics Summit , silicon photonics , photonics

カスタムIC／ミックスシグナル

Spectre Tech Tips: Spectre Strobe機能の使用

Spectre®回路シミュレータをご利用のお客様で、SpectreのStrobe機能で対応可能な用途にmaxstep機能を使用しているケースが時々見受けられます…

• 1 min read
Fast Fourier Transform , ADE Explorer , strobe , Spectre Circuit Simulator , Virtuoso Analog Design Environment , Virtuoso IC6.1.8 , japanese blog , ADE Assembler

Academic Network

Organic Printed Electronics PDK Education Kit Available Now

The Virtuoso Education Kit has just been released and now there is already a new…

• 3 min read
Cadence Academic Networ , Education Kits , Virtuoso , Organic Printed Electronics

Computational Fluid Dynamics

Lunch & Learn and Women in Engineering at the ASME Turbo Expo 2022

Cadence is looking forward to meeting with you at the 'Lunch and Learn' and 'Women…

• 2 min read
CFD , Lunch and Learn , turbomachinery , ASME Turbo Expo , Pointwise , Turbo Thursday , Cadence Fidelity , women in engineering , engineering , simulation software , NUMECA , Women in CFD

Breakfast Bytes

Arm SystemReady Compliance Using Emulation

Yesterday in my post Cadence and Arm I wrote about how Cadence has worked with Arm…

• 3 min read
AVIP , Perspec , systemready , Palladium , Emulation , ARM

System, PCB, & Package Design 

ASCENT: Training Insights: Get Rid of Design Errors in Allegro System Capture

With thousands of components connected across a multi-layered board, anticipating…

• 5 min read
System Capture , 17.4 , Design Rule Checker , 17.4-2019 , Training Insights , Allegro System Capture , ASCENT , Schematic

Analog/Custom Design

Virtuoso Meets Maxwell: Improving Manufacturability and Yield

This blog is to announce the official release of the Fillet capability. The Fillet…

• 2 min read
fillet , metal density , Virtuoso Meets Maxwell , Virtuoso RF Solution , T connections , Improving Manufacturability and Yield , Virtuoso RF , tapered traces

Breakfast Bytes

Cadence and Arm

I've been working with Arm for longer than Cadence has. In fact, I was working with…

• 6 min read
vlsi technology , cerebrus , Innovus , ARM

Computational Fluid Dynamics

Less than a Minute to Water-tight Geometry Using Fidelity CFD AutoSeal

Cadence Fidelity CFD offers AutoSeal technology, a geometry clean-up tool for faster…

• 3 min read
CFD , AutoSeal , geometry cleanup , Pointwise , CAD preparation , Fidelity CFD , engineering , simulation software , NUMECA , preprocessing

System, PCB, & Package Design 

Frequency Matters Podcast: System Analysis Solutions

By Sherry Hess Recently I posted a blog on LinkedIn called "High Tech Everything…

• less than a min read

Breakfast Bytes

The 2022 Kaufman Dinner

On May 12th, it was the Kaufman Award Ceremony and Banquet at which Cadence's CEO…

• 5 min read
kaufman dinner , Kaufman Award , Anirudh Devgan , kaufman award 2021

Breakfast Bytes

Sunday Brunch Video for 15th May 2022

https://youtu.be/F-dN8wy-iNc Made at Steve Brown's "moving to San Diego party" …

• less than a min read
sunday brunch

Academic Network

Searching on Cadence Support Is Now Even Easier!

The Cadence Learning and Support Portal is useful to academia in many ways: Online…

• 1 min read
Cadence Academic Network , Cadence Online Support , online training , university program

Breakfast Bytes

New Book: Hyperscale Computing Trends 2022

Cadence has a new book out. Written by Frank Schirrmeister and myself, it is called…

• 3 min read
hyperscaler , Schirrmeister , McLellan , book

Verification

Demystifying CXL.cache

If you have worked with Peripheral Component Interconnect Express (PCIe) in the past…

• 3 min read
CXL , Functional Verification , pcie 5 , VIP , PCIExpress , coherency , verification

System, PCB, & Package Design 

IC Packagers: Three Reasons for Allegro Package Designer Plus Users to Move to OrCAD…

The HotFix 028 of our 17.4-2019 release was rolled out at the end of March and is…

• 1 min read
IC Packaging , APD , IC Packaging & SiP design , IC Packagers , Allegro Package Designer , 17.4-2019 , 17.4 QIR4

Breakfast Bytes

What Is High-NA EUV?

I'm sure you know that the lowest levels of ICs fabricated at the most advanced nodes…

• 5 min read
asml , imec , SPIE , high-na euv , EUV
CDNS - Fix Layout Hompage