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Cadence Certifies AI-Driven Reference Flows for Intel 18A-P and Intel 14A

The expanded Cadence-Intel Foundry collaboration delivers silicon-proven digital…

Corporate
• 3 min read
DAC , Design IP , featured , DAC 2026 , AI-Driven Design

Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Digital Design

Voltus Voice: Demystifying ESD — 5 Types of Checks to Bump up Your ESD Protectio…

This blog discusses the different Voltus electrostatic discharge (ESD) checks in…

• 4 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Full-Chip , ESD

Analog/Custom Design

Start Your Engines: Seven Habits of Highly Efficient Mixed Signal Verification E…

This blog shares insights on the seven best practices that should be followed by…

• 8 min read
AMS-Designer , mixed-signal methodology , Start Your Engines , Virtuoso , mixed signal , AMS Verification , mixed-signal verification

Verification

PSS2.0 is Out – Reflections on the Role of a Standard

We all know that a common language is the basis for every collaborative activity…

• 3 min read
portable test and stimulus standard , standardization , pss2.0 , pss

System, PCB, & Package Design 

(P)SpiceItUp: Search by Category, Description, or Function with PSpice Part Sear…

As a designer, your requirement at the early stages of schematic design is quite…

• 4 min read
17.4 , cadence , OrCAD Capture , PSpiceA/D , logical design , Capture CIS , (P)SpiceItUp , 17.4-2019 , OrCAD , Part Search , simulation , Schematic

Breakfast Bytes

Embracing a Zero Trust Security Model

A couple of months ago, the National Security Agency (NSA) published a document titled…

• 4 min read
security , nsa , zero trust

Breakfast Bytes

Brian Jackson Introduces a Mystery Product at IMAPS (Shh, It's OrbitIO)

I have been criticized in the past for calling OrbitIO the "red-headed stepchild…

• 6 min read
system in package , 3DIC , OrbitIO

Verification

CCIX Coherency: Verification Challenges and Approaches

Cache coherency is not a new concept. Coherent architectures have existed for many…

• 2 min read
SoC verification , ccix , PCIe , coherency , CXS

Verification

PSS 2.0 Is Available and Driving Portable Stimulus to the Mainstream!

Three years ago, PSS (Portable Test and Stimulus) specification 1.0 was released…

• 2 min read
Perspec , pss , portable stimulus , verification

Breakfast Bytes

Update: Pointwise, PCIe, RISC-V

This is another of my occasional update posts, covering changes to recent posts that…

• 3 min read
risc-v , pcie 5 , Pointwise , PCIe

RF /マイクロ波設計

μWaveRiders:Cadence AWR ソフトウェアでの強化されたロードプル

Team RF "μWaveRiders" ブログシリーズはCadence AWR RF製品のためのショーケースです。月ごとの話題はCadence AWR Design…

• less than a min read
PCB , source impedance , load impedance , AWR Design Environment , Load Pull analysis , Load Pull data , Load Pull template , RF design , AWR Microwave Office , PA , japanese blog

Breakfast Bytes

Sunday Brunch Video for 18th April 2021

https://youtu.be/afv9_fRCrq8 Made at Target Oakridge (camera Ziyue Zhang) Monday…

• less than a min read
sunday brunch

Analog/Custom Design

Virtuoso Meets Maxwell: Creating Connectivity Between Die and BGA Package for IC…

Before the creation of die and package layout can begin, logical connectivity between…

• 5 min read
IC , package , Footprint , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Package Design in Virtuoso , Allegro Package Designer Plus , BGA , die , OrbitIO , SiP Layout Option , ICADVM20.1 , Ball , Custom IC , bump

RF Engineering

μWaveRiders: Enhancing Load Pull with Cadence AWR Software

The Cadence AWR Design Environment platform V15 offers enhanced load pull capabilities…

• 5 min read
PCB , source impedance , load impedance , AWR Design Environment , Load Pull analysis , Load Pull data , Load Pull template , RF design , AWR Microwave Office , PA

Analog/Custom Design

Virtuosity: What’s New on the Cadence Learning and Support Portal – Virtuoso Layout…

Cadence Learning and Support portal has introduced a new one-stop learning resource…

• 3 min read
Virtuoso , Virtuosity , ICADVM20.1 , Custom IC Design , RAKs , Virtuoso Layout Suite , Custom IC , IC6.1.8 , Virtuoso Layout Suite XL

Spotlight Taiwan

Palladium Z2和Protium X2 雙重奏(Dynamic Duo)引擎系統、邁向驗證新時代 !

原文出處: Dynamic Duo 2: The Sequel 作者: Paul McLellan 有一個故事，可能是虛構的，關於一位編劇在好萊塢找人投資影片的故事…

• less than a min read
dynamic duo , prototyping , protium x2 , palladium z2 , FPGA prototyping , taiwanese blog , software development , firmware development

Computational Fluid Dynamics

This Week in CFD

This Week in CFD reached convergence long before I had exhausted the two-week backlog…

• less than a min read
CFD , Pointwise , Computational Fluid Dynamics

Breakfast Bytes

Evolving Maturity in Ransomware

I recently attended a Black Hat seminar titled The Evolving Maturity in Ransomware…

• 6 min read
security , ransomware , cybersecurity

カスタムIC／ミックスシグナル

Spectre Tech Tips: リークパスによる電流ホットスポットの検出

回路設計において、誤った接続が望ましくないリークパスを引き起こし、結果として電流のホットスポットとなる可能性があります。こういった電流のホットスポットはSpectre…

• less than a min read
Dynamic design checks , Spectre design checks , leakage path detection , Spectre , dyn_dcpath , japanese blog , dyn_subcktpwr

Computational Fluid Dynamics

AeroDelft Pushes the Airline Industry towards a Sustainable Future with Liquid Hydrogen…

AeroDelft is a student team at the forefront of sustainable aviation. While based…

• less than a min read
CFD , Computational Fluid Dynamics
CDNS - Fix Layout Hompage