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Corporate News

The Autonomous Chip-to-System Engineer Has Arrived

How Cadence, in collaboration with NVIDIA, is building the industry's first silicon…

Corporate
• 4 min read
AuraStack AI Super Agent , DAC , featured , agentic ai , NVIDIA

Corporate News

Cadence’s Agentic AI Design Vision Takes Center Stage at DAC

AI infrastructure demands are changing what semiconductor design must solve. The…

Corporate
• 4 min read
AuraStack AI Super Agent , featured , agentic ai , DAC 2026 , ChipStack AI Super Agent

Corporate News

AI Infrastructure Starts Beyond the Chip

Why Advanced Packaging and PCB Design Have Become the Next Frontier of Innovation…

Corporate
• 8 min read
chip , featured , AI infrastructure , agentic ai , packaging

Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio
cdns - all_blogs_categories

Blog - Post List
Latest blogs

PCB、IC封装：设计与仿真分析

汽车 EMC 问题一览

汽车 EMC 问题是仅次于尾气排放和交通噪音的第三大车辆污染形式。与传统的内燃机汽车相比，电动或混合动力汽车更容易受到汽车 EMC 问题的困扰。本文将探讨汽车常见…

• less than a min read
Chinese blog , EMI , Clarity 3D Transient Solver , FDTD , FEM , EMC , 中文 , 电磁仿真 , 系统分析 , 汽车 , 智能系统设计 , Clarity 3D Solver

カスタムIC／ミックスシグナル

Virtuoso Studio: デザイン、プランニング、解析 – コインの3つの側面、エピソード2

当社の新しい AI 搭載カスタム設計ソリューション Virtuoso Studio は、我々の30年にわたる業界の知識とリーダーシップを活用し、革新的な機能、比類のない生産性を実現する再構築されたインフラストラクチャ…

• less than a min read
Virtuoso Studio , japanese blog , Custom IC Design , Virtuoso Layout Suite , Design Planning and Analysis , Floorplanner

Learning and Support

Cadence Welcomes New Member Sumedha IT to the Certified Training Partner Program

The semiconductor industry requires a highly skilled workforce and necessitates recent…

• 2 min read
Cadence training , Training Partners

Academic Network

Cadence on Campus - Carnegie Mellon University

Cadence continues to build strong relationships with academia to foster the next…

• 1 min read
Cadence Academic Network , Carnegie Mellon University , Future Innovators

Verification

Why Do You Need a Simulator-Friendly Debug Tool for UVM Debug?

UVM Testbench Today In 2011, UVM1.0 was introduced to the industry. It has already…

• 6 min read
uvm , debug , Testbench simulation , testbench , VerisiumDebug

PCB設計／ICパッケージ設計

PCB Westの来場者を驚愕させたCadenceの生成AIによるPCB設計ソリューション

By Patrick Davis and Amlendu Shekhar Choubey, Product Management Directors, PCB,…

• less than a min read
Allegro X AI , Generative AI , OrCAD , PCB design , OrCAD X , japanese blog , allegro x , Allegro

カスタムIC／ミックスシグナル

Virtuoso Studio: Navigator クエリを使用してデザインをよりよく整理

我々の新しいAIを活用したカスタムデザインソリューションである Virtuoso Studioは、我々の30年にわたる業界の知識とリーダシップを活用し、革新的な機能…

• less than a min read
Virtuoso Schematic Editor , Virtuoso Studio , Navigator , japanese blog , Navigator queries , IC23.1

カスタムIC／ミックスシグナル

Virtuoso Meets Maxwell: EMX Planar 3D Solverでのメッシュの確認

'Virtuoso Meets Maxwell'はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です…

• less than a min read
Cadence blogs , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Electromagnetic analysis , Virtuoso , EMX , japanese blog , Custom IC Design , Virtuoso Layout Suite , Custom IC

Computational Fluid Dynamics

Understand the Physics of Re-Entry Vehicles Using Numerical Modeling and Simulat…

Reproducing the atmospheric conditions of planets like Mars is challenging. To successfully…

• 4 min read
hypersonics , Pointwise , Computational Fluid Dynamics , Cadence Fidelity , Aerospace Engineering , Mars , simulation software , Numerical Methods , vehicle reentry

Analog/Custom Design

Virtuoso Studio IC23.1 ISR2 Now Available

Virtuoso Studio IC23.1 ISR2 production release is now available for download.

• 1 min read
Cadence blogs , Virtuoso Studio , IC Release Announcement blog , IC Release Blog , Cadence Community , IC23.1

Verification

Enhancing Network Security with MacSec: Protecting Ethernet Communications

The evolution of technology has led to a rapid increase in data transmission over…

• 2 min read
security , Automotive , Ethernet 800G , Verification IP , Ethernet VIP , Functional Verification , System Design and Verification , VIP , Ethernet standards , Automotive Ethernet , encryption , Ethernet , MacSec , Ethernet 400G , verification

System, PCB, & Package Design 

Advancing 112G SI/PI Techniques (Knowledge) by Catching the Advanced Signal Integrity…

If you missed the Signal Integrity Journal Advanced Signal Integrity Forum, broadcast…

• 2 min read
SI , PI , ddr5 , high-speed interconnect , Micron , chiplet , Apex , Multi-Chiplet Package , Power Integrity , Signal Integrity , 112g , system-level analysis , Sigrity , Signal Integrity Journal

RF Engineering

Designing a 30MHz to 1000MHz 10W GaN HEMT Power Amplifier

By David Vye, Senior Product Marketing Manager, AWR, Cadence When designing multi…

• less than a min read
featured , AWR Design Environment , Power amplifier , RF design , microwave office

System, PCB, & Package Design 

PCB West Visitors Wowed by Cadence’s Generative AI PCB Design Solutions

By Patrick Davis and Amlendu Shekhar Choubey, Product Management Directors, PCB,…

• 1 min read
Generative AI , OrCAD , PCB design , Allegro

Analog/Custom Design

Virtuoso Meets Maxwell: Virtuoso and Allegro SKILL for Efficient Co-Design

In today's dynamic landscape of design, collaboration between different design elements…

• 7 min read
Virtuoso Studio , Edit-in-Concert , Co-Design , Virtuoso Meets Maxwell , Virtuoso RF Solution , Allegro Package Designer Plus , Virtuoso Multi-Technology Solution , SKILL APIs , SKILL , Allegro , VMM

Analog/Custom Design

Spectre Tech Tips: Selecting Limits for Parameter Value Warnings

You can accept Cadence default soft limits that determine when you receive warning…

• 7 min read
param , Circuit simulation , Spectre Circuit Simulator , Spectre , check , verification

SoC and IP

Cadence Targets Automotive Market Demands with UCIe

Cadence has become a contributor-level member of the Automotive Working Group in…

• 2 min read
ucie , IP , chiplets , Design IP and Verification IP

Analog/Custom Design

Virtuoso Studio: Organize Your Designs Better with Navigator Queries

Navigator queries let you group objects into sets that meet specific conditions,…

• 2 min read
Virtuoso Schematic Editor , Virtuoso Studio , Navigator , Navigator queries , IC23.1

Corporate News

Alif Is Creating SoC Solutions for Machine Learning with Cadence and Arm

Alif Semiconductor is bridging the gap between standard microcontrollers and high…

• 2 min read
Tempus , designed with cadence , machine learning , digital flow , ARM , AI
CDNS - Fix Layout Hompage