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Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

IC Packagers: Automating Your LVS Text Label Generation

If you are using Allegro Package Designer Plus with the Silicon Layout option to…

• 4 min read
17.4 , IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

How Do You Run One Architecture on Another?

You probably already heard that going forward some Macs are going to be running on…

• 5 min read
Intel , Apple , dynamic translation , jit

Breakfast Bytes

Sunday Brunch Video for 5th July 2020

https://youtu.be/qimXaFAFh6w Made for July 4th (camera me) Monday: Yesterday Was…

• less than a min read
sunday brunch

カスタムIC／ミックスシグナル

Virtuosity: Virtuoso ADE ユーザビリティ改善に関する最新情報

私たちの世界では、ユーザビリティとは、製品を使いやすくし、アクセスを簡単にし、視覚的に魅力的なものにすることです。私たちは製品の使い勝手を改善するため、絶え間なく努力します…

• 2 min read
ADE Explorer , Rapid Adoption Kit , ViVA , ADE Design Environment , Virtuosity , usability , japanese blog , Custom IC Design , ADE Assembler

Analog/Custom Design

Start Your Engines: The Blog-o-Meter Check

A summary of the blogs published in the Start Your Engines blog series.

• 2 min read
CLIPS , mixed signal design , Functional Verification , AMS Designer , Unified Netlister , AMSD Flex Mode , mixed-signal verification

Analog/Custom Design

Virtuosity: Good News for our Japanese Readers

In this blog, I’m going to share some great news for our Japanese readers. Let's…

• 3 min read
Trunk generation , ICADVM18.1 , AMS Designer , VPR , layout XL , Virtuoso , Japanese blogs , Virtuosity , advanced nodes , ASMD Flex Mode , Virtuoso Layout Suite , Custom IC

定制IC芯片设计

Virtuosity：大小一样的乐高积木，能拼出大师级杰作吗？

您需要使用不同大小和类型的积木块，才能拼出大师级的乐高杰作，基于WSP的设计也是如此，它需要将具有不同WSSPDef周期的多个模式的布线区域拼接在一起。接下来，让我们一起来探讨如何实现这一目标…

• less than a min read
Chinese blog , ICADVM18.1 , cadence , WSP , Advanced Node , Local regions , Layout Suite , width spacing patterns , Layout , Virtuoso , Virtuosity , usability , Custom IC Design , ux , WSSPDef

Breakfast Bytes

July 4th: The Glorious Revolution

The Fourth of July is coming up. Cadence is closed for a four-day weekend, so this…

• 8 min read
offtopic

Breakfast Bytes

Japanese Arm-Powered Supercomputer Takes the TOP500 Crown

Twice a year, around the middle of the year (that would be now) and around the end…

• 4 min read
fugaku , top500 , ARM , supercomputer

Analog/Custom Design

Virtuoso IC6.1.8 ISR12 and ICADVM18.1 ISR12 Now Available

The IC6.1.8 ISR12 and ICADVM18.1 ISR12 production releases are now available for…

• 3 min read
Cadence blogs , ICADVM18.1 , ADE Explorer , EM Solver , Virtuoso RF Solution , IC Release Announcement blog , Virtuoso , IC Release Blog , Virtuoso Layout Suite EXL , Virtuoso Layout Suite , ADE Verifier , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL

Breakfast Bytes

Alessandra Nardi Receives Marie Pistilli Award for Women in EDA

Cadence's Alessandra Nardi, software engineering group director, is the 2020 recipient…

• 6 min read
Automotive , DAC , functional safety , alessandra nardi , marie pistilli award

System, PCB, & Package Design 

IC Packagers: Accelerate Complex Degassing with 17.4

Degassing, other times called outgassing, is a common operation in IC package and…

• 6 min read
IC Packaging , Allegro Package Designer

System, PCB, & Package Design 

BoardSurfers: Good News for Japanese Readers

In this blog, I’m going to share some great news for our Japanese readers. Let's…

• 1 min read
PCB , 17.4 , OrCAD Capture , APD , PSPICE , Allegro PCB Editor

Life at Cadence

The Returnship Journey — Part 1

Life happens! Depending on the circumstances, we must sometimes press the “pause…

• 3 min read
inclusion , GPTW , WorkLifeBalance , WomenAtCadence , returnship

定制IC芯片设计

Virtuoso Meets Maxwell: 电磁分析魔法化

我们为什么要在virtuoso RF 解决方案中进行EM Analysis？ 如果您看过魔术表演，就会知道它就像魔术师一样可以把不可能变成可能。 如果您曾因为繁琐的EM集成而烦恼…

• 1 min read
EM Analysis , Chinese blog , ICADVM18.1 , Virtuoso New Design Platform , video , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Electromagnetic analysis , RF design , Virtuoso Layout Suite , Chinese blogs

Learning and Support

Looking to Learn About Virtuoso ADE Product Suite? We’ve Got a Webinar for You!

Interested in the Virtuoso ADE Product Suite? Cool! We’ve got a great webinar for…

• less than a min read
training , Virtuoso ADE , webinar , Virtuoso , Cadence support

Digital Design

Voltus Voice: A New Blog Series to Discover the “Power” Within

Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies…

• 3 min read
Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , video , Power Integrity , training , Voltus , Digital Implementation , Power Sigonff , design closure , IR drop , RAKs , EMIR

Digital Design

Library Characterization Tidbits: Did Your Search for Constraints Fail?

While using the Cadence Liberate Characterization solution or the Liberate Variety…

• 4 min read
search bound , Liberate Variety , library characterization , glitch metric , Library Characterization Tidbit , Digital Implementation , final state threshold , troubleshooting , Liberate , Constraints , Liberate Characterization Portfolio , glitch tolerance

カスタムIC／ミックスシグナル

Start Your Engines: UNLでアナログ・ブロックにSpectreネットリストを生成する理由と方法

Cadence® Spectre® AMS Designer は、高いパフォーマンスのミックスシグナル・シミュレーション・システムです。複数エンジンの使用や、さまざまなプラットフォームから実行できる機能により…

• less than a min read
AMS Designer , Mixed Signal Verification , Unified Netlister , mixed signal , japanese blog , analog/mixed signal , AMS UNL
CDNS - Fix Layout Hompage