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Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
Corporate 30 Jun 2026 • 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

  • All 6432
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  • Analog/Custom Design 804
  • Artificial Intelligence 28
  • Cloud 23
  • Computational Fluid Dynamics 374
  • Data Center 60
  • Digital Design 465
  • Learning and Support 63
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1017
  • Verification 1329
  • Cadence Japan 18
  • Physical Systems Simulation 24

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Academic Network

ESSCIRC and ESSDERC in Lausanne

Since the year 2000, the European Solid-State Device Research Conference (ESSDERC…

ChristinaB 16 Sep 2016 • 2 min read
Cadence Academic Network , esscirc , essderc

Computational Fluid Dynamics

Masten Space Systems: Reuseable Space Craft Innovation With Cadence CFD Software

Until very recently, rockets that launched satellites into orbit were completely…

AnneMarie CFD 16 Sep 2016 • 5 min read

Breakfast Bytes

Are These Codecs Any Good? Netflix Tests Them

A codec compresses data for transmission. The first codec I had any close encounter…

Paul McLellan 16 Sep 2016 • 5 min read
GSM , audio codec , H.265 , codec , netflix , mobile , h.264 , video codec , Breakfast Bytes

Breakfast Bytes

What’s for Breakfast? Preview September 19th to 23rd (video)

https://youtu.be/KKiIDaN-3CE Monday: At CDNLive Boston I moderated a panel session…

Paul McLellan 15 Sep 2016 • less than a min read
cdnlive tel aviv , Paul McLellan , CDNLive , debug , mellanox , VIP , MIPI , Power Integrity , i2c , cdnlive boston , mipi devcon , Indago , Signal Integrity , cdnlive israel , I3C , what's for breakfast? , protocol verification , Breakfast Bytes , verification

Breakfast Bytes

Emulation Productivity: Beyond the Specs

At CDNLive in Boston, Andrew Ross of AMD presented a wealth of practical information…

Paul McLellan 15 Sep 2016 • 5 min read
CDNLive , palladium z1 , Protium , Palladium , cdnlive boston , Emulation , FPGA prototyping , Breakfast Bytes

Academic Network

Increasing Functional Verification Coding Process Efficiency

In EDA you traditionally have to know several modelling languages for several domains…

Daniel Bayer 14 Sep 2016 • 3 min read
eclipse , Cadence Academic Network , Functional Verification , DVT , Coding Efficiency

Breakfast Bytes

Everything That's New About Ethernet

IEEE 802.3 is the standard number for various flavors of Ethernet. With Ethernet…

Paul McLellan 14 Sep 2016 • 6 min read
Ethernet standards , Ethernet , 802.3 , IEEE , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Training Different Networks Using Hierarchical CNN

In this week's Whiteboard Wednesdays video, Michelle Mao follows up on last week…

References4U 13 Sep 2016 • less than a min read
Whiteboard Wednesdays , IP , Tensilica

Breakfast Bytes

DARPA: All Must Have Prizes

At CDNLive Boston, the invited keynote was by Dr. Bill Chappell of DARPA's Microsystems…

Paul McLellan 13 Sep 2016 • 4 min read
CDNLive , cdnlive boston , robotics , autonoous vehicles , craft , microsystems technology office , darpa

Breakfast Bytes

Electronic Design Automation Handbook

Way back in 2006, Luciano Lavagno, Lou Scheffer, and Grant Martin, all then at Cadence…

Paul McLellan 12 Sep 2016 • 4 min read
TCAD , Electronic Design Automation , system design , EDAC , Testing , implementation , Circuit Design , process design , Breakfast Bytes , verification , book

Breakfast Bytes

Facebook's Aquila Flies...and OpenCellular

In Barcelona in February I attended a "keynote' with Mark Zuckerberg which was actually…

Paul McLellan 9 Sep 2016 • 4 min read
aquila , Facebook , opencellular , zuckerberg , internet.org

Breakfast Bytes

What’s for Breakfast? Preview September 12th to 16th (video)

https://youtu.be/eDeD0mg7D54 Monday: My review of Electronic Design Automation…

Paul McLellan 8 Sep 2016 • less than a min read
CDNLive , palladium z1 , AMD , H.265 , IEEE 802.3 , cdnlive boston , Ethernet , Emulation , codec , netflix , h.264 , vp9 , video codec , darpa

Breakfast Bytes

Cadence's History with MIPI

I talked last week to Kevin Yee, Sachin Dhingra, and Moshik Rubin about the history…

Paul McLellan 8 Sep 2016 • 6 min read
Automotive , MIPI , mipi devcon , mobile

Whiteboard Wednesdays

Whiteboard Wednesdays - Benefits of Cadence Hierarchical CNN Design

In this week's Whiteboard Wednesdays video, Michelle Mao talks about Cadence hierarchical…

References4U 7 Sep 2016 • less than a min read
Whiteboard Wednesdays , IP , Tensilica , CNN

Breakfast Bytes

SiFive: a RISC-V Fabless Semiconductor Company

A couple of weeks ago I talked to Krste Asanović and Jack Kang of SiFive. Jack is…

Paul McLellan 7 Sep 2016 • 3 min read
risc-v , fabless , sutter hill ventures , freedom unleashed , freedom everywhere , sifive , foundry

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? New Concurrent Team Design Capability (Reason 2…

Use teamwork to get off the critical path! When (not if) change happens or scope…

mcatramb91 6 Sep 2016 • 3 min read
Allegro 17.2 , Symphony , Real Time Design , PCB design , Why Move Up to 17.2

System, PCB, & Package Design 

Cadence Online Support — Empowering Learning! New Features from July 2016

Lots of documents are posted on Cadence Online Support on regular basis. Let us take…

Jasmine 6 Sep 2016 • 2 min read
cadence online , "PCB design" , application note , Allegro

Breakfast Bytes

CDNLive Boston Overview

CDNLive Boston took place last week. It is really CDNLive East Coast, and there were…

Paul McLellan 5 Sep 2016 • 6 min read
CDNLive , Power Integrity , cdnlive boston , Signal Integrity , Breakfast Bytes

Breakfast Bytes

RISC-V Gathering Momentum

I've been writing quite a bit about RISC-V (pronounced "risk five") since I think…

Paul McLellan 2 Sep 2016 • 4 min read
krste asonovic , risc-v , codasip , NVIDIA , google , andes , cortus , Breakfast Bytes , sifive , hp enterprise
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