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Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P
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Blog - Post List
Latest blogs

PCB、IC封装：设计与仿真分析

汽车行业合规与功能安全指南：ISO 26262 标准出台十周年

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章“ Happy 10th Birthday ISO…

• less than a min read
Chinese blog , 中文 , 功能安全 , 汽车 , ISO 26262

Digital Design

Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis…

A Logic Synthesis is a process of optimizing the design's area, timing, and power…

• less than a min read
Genus , Flows , Logic Design , Optimize , Synthesis

Breakfast Bytes

Linley: Western Digital's RISC-V Strategy

Western Digital acquired SanDisk in 2016. In 2017, Martin Fink, then the CTO of Western…

• 3 min read

PCB設計／ICパッケージ設計

BoardSurfers: IPC-2581の利用によるレイヤースタックアップデータの受け渡し

設計意図やスタックアップ情報を設計の初期段階のうちに製造部門や製造委託先と共有しておけば、製品設計に影響を与え製品納入を遅らせてしまうような製造やアセンブリ関連の問題を回避することができます…

• less than a min read
PCB manufacturing , BoardSurfers , IPC-2581 Consortium , 17.4-2019 , japanese blog , Allegro PCB Editor , IPC-2581 , Allegro

Breakfast Bytes

Sunday Brunch Video for 8th May 2022

https://youtu.be/xADMKcqKLNg Made on Communication Hill with Sheep (camera Carey…

• less than a min read
sunday brunch

Digital Design

Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal…

No matter how your name is spelt in different countries, and how they say it, once…

FormerMember • 1 min read
digital badge , conformal , training bytes , online training

PCB、IC封装：设计与仿真分析

如何建立一个数据中心：全靠 SerDes和散热

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “How to Build a Data Center…

• less than a min read
Chinese blog , 热分析 , celsius , 以太网 , PCIe , 中文 , 系统分析 , SerDes , 散热 , 数据中心

Digital Design

Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)?…

• less than a min read
Genus , gui , place and route , highlighted objects , physical implementation

Breakfast Bytes

An Interview with Morris Chang

A couple of weeks ago, Morris Chang, the founder of TSMC and, for a long time (twice…

• 4 min read
TSMC , Morris Chang

System, PCB, & Package Design 

ASCENT: Reasons to Move to 17.4-2019 HotFix SPB17.40.028 of Allegro Pulse

HotFix SPB17.40.028 of 17.4-2019 of Allegro® Pulse is out and is available for download…

• 5 min read
collaboration , data platform , Team design , QIR4 , 17.4-2019 , Allegro Pulse , Allegro System Capture , ASCENT

PCB、IC封装：设计与仿真分析

AWR：智能射频设计

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “ AWR: Intelligent RF Design…

• 1 min read
射频 , 5G , RF , 微波 , Chinese blog , awr , 中文 , awr v16

Breakfast Bytes

A History of Cadence in the Cloud

Cadence Cloud started before there even was a cloud. We just didn't call it Cadence…

• 7 min read
cloud , special post , cadence cloud

Verification

Enflame Accelerates the DFT and DFD Verification using Palladium

DFT (Design for Testability) provides the much-needed support to the manufacturers…

• 5 min read

System, PCB, & Package Design 

This Month in IDA

This month the In-Design Analysis (IDA) team kicked off its new blog program with…

• 1 min read
in-design analysis , Signal Integrity , electromagnetic , microwave design , thermal

PCB、IC封装：设计与仿真分析

OMNIS – 如何在汽车领域应对当今和未来的多物理场仿真挑战？

本文作者：Yannick Baux, Cadence产品研发总监 space 汽车行业一直使用 CFD 工具来设计和优化车辆的各个方面，从外部空气动力学到降噪，再到热管理…

• less than a min read
CFD , Chinese blog , 网格生成 , 流体力学 , 计算流体动力学 , CFD应用 , 仿真 , 中文 , 系统分析 , 汽车 , 多物理场仿真 , Omnis

Academic Network

Virtuoso Education Kit Available Now

The Cadence Education Kit initiative runs at full steam! After the release of the…

• 2 min read
Cadence Academic Network , Education Kit , Virtuoso , analog design

Breakfast Bytes

Always On at D&R

At the recent D&R IP-SoC Day 2022, Amol Borkar presented Designing the Next Ultra…

• 5 min read
always on , vision p1 , Tensilica , aon

PCB、IC封装：设计与仿真分析

如何在PCB设计中进行DDR布线？

DDR布线技术的重要性 在如今的印刷电路板设计中，双数据速率（DDR）存储器非常普遍。许多设计都会用到DDR存储器配置的不同版本，这需要在布局中使用特定的布线模式…

• less than a min read
Chinese blog , 布线 , PCB设计 , 中文 , DDR , Allegro PCB Editor , Allegro

Breakfast Bytes

ESD Alliance CEO Outlook 2022

Last week was the ESD Alliance CEO Outlook. It was hosted by Keysight (fka Agilent…

• 13 min read
keysight , cadence , ceo outlook , Siemens , ARM , D2S , esd alliance
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