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Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Formally Verifying Processor Security

Intel has had a couple of major events that totally changed their attitude to verification…

• 4 min read
Intel , Jasper User Group , formal , Jasper , JasperGold

PCB、IC封装：设计与仿真分析

RF设计直播课程：如何提高RF前端模块封装设计的迭代效率

大家好，我是Principal Customer Engagement Engineer江亮，从事射频前端模块设计七年，先后受聘于Qorvo，RDA等多家射频半导体研发企业…

• less than a min read
PCB , RF , Chinese blog , PCB设计 , 封装设计 , 直播网课 , 射频前端 , Sigrity , Allegro , 专家培训

Academic Network

CADathlon at ICCAD 2019

Last week, I visited the Cadathlon@ICCAD event at the 2019 International Conference…

• 2 min read

System, PCB, & Package Design 

BoardSurfers: What's Happening Around 17.4-2019?

Allegro and OrCAD 17.4-2019 was released on October 18 and we have since then been…

• 2 min read
17.4 , PCB Editor , SKILL

Breakfast Bytes

OpenROAD: Open-Source EDA from RTL to GDSII

OpenROAD is a DARPA program to attempt to build a no-human-in-the-loop EDA flow,…

• 6 min read
ucsd , dod , openroad , andrew kahng , darpa

Academic Network

Successful Speaker Event—Engaging with Professor in Shanghai

The Cadence Academic Network hosted an Academic Speaker Series event, in collaboration…

• 2 min read
university , Cadence Academic Network , academia , university program

Breakfast Bytes

What Does P≠NP Mean?

Recently I wrote about computational software and said that EDA algorithms are all…

• 6 min read
NP-complete , computational software , np-hard

Analog/Custom Design

Virtuosity: Usability Enhancements in the Property Editor

Goes without saying that the Property Editor is the most frequently used feature…

• 2 min read
ICADVM18.1 , Virtuoso Layout Suite L , Property Editor , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

Die-to-Die Interconnect: The UltraLink D2D PHY IP

One of the big trends that has been happening somewhat below the radar is the growth…

• 5 min read
system in package , SiP , chiplet , more than Moore , 3D packaging

System, PCB, & Package Design 

IC Packagers: Plan Your Escape with Modernized Structures

Many of you, our regular readers, are familiar with via structures. These reusable…

• 3 min read
17.4 , APD

Life at Cadence

Asking Our Employees: What Makes Us Great in Europe?

As the project manager of our global Great Place to Work programs, I’ve had the opportunity…

• 6 min read
Culture , Community , giving back , GPTW , great place to work

Analog/Custom Design

Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part III

This is the third blog in the multi-part series that aims at providing in-depth details…

• 8 min read
ICADVM18.1 , Virtuoso Layout EXL , Virtuoso RF , Layout EXL , Electromagnetic analysis , Virtuoso , Custom IC Design

System, PCB, & Package Design 

What's in a Name? From Allegro EDM to Pulse in 17.4-2019

Allegro EDM (Engineering Data Management) 17.4-2019 is out! So, what's in it for…

• 4 min read
allegro edm , what's new , 17.4-2019 , PCB design , Pulse

Breakfast Bytes

The 2019 Jasper User Group

Last week was the Jasper User Group meeting, the biggest annual gathering of formal…

• 4 min read
Jasper User Group , formal , Jasper , JasperGold , Formal verification

Academic Network

Exciting Academic News on OrCAD

There’s some exciting news about the Cadence OrCAD® Software , especially for academics…

• 2 min read
PCB , academia , Contest , OrCAD , university program

PCB、IC封装：设计与仿真分析

隐藏在PCB设计中的七个DFM问题

本文由Cadence的北美经销商EMA Design Automation撰写。 space 当我们完成设计并将其送到制造厂后，如果我们的产品存在大量可制造性设计…

• less than a min read
Chinese blog , DesignTrue DFM Technology , 可制造性设计 , PCB设计 , 中文 , DFM , Allegro

Breakfast Bytes

OpenTitan: Secure Boot with a Silicon Root of Trust

At HOTCHIPS last year, Google presented its security processor Titan. You can read…

• 3 min read
opentitan , open source hardware , google , open source

Digital Design

Library Characterization Tidbits: Reasons to Start Following This New Blog Serie…

Library Characterization Tidbits is a blog series aimed at providing insight into…

• 1 min read
Liberate AMS , videos , Liberate LV , Liberate Variety , library characterization , Application Notes , Liberate MX , training bytes , Liberate , Liberate Characterization Portfolio , RAKs

Breakfast Bytes

Computational Software

This is the third post in a series on computation in EDA and adjacent markets. The…

• 4 min read
computational software
CDNS - Fix Layout Hompage