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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
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Blog - Post List
Latest blogs

Verification

DVCon 2012 Video: Product Engineer Chris Komar Reviews the Tutorial on Formal Ap…

In this interview Product Engineer Chris Komar recaps the tutorial on formal apps…

• less than a min read
Low Power , Joe Hupcey III , ABV , metric driven verification (MDV) , Functional Verification , Formal Analysis , formal , formal apps , Chris Komar , DVcon , apps , assertion synthesis , assertions , IEV , Assertion-Driven Simulation , Formal verification , IFV , verification , Assertion-based verification

Analog/Custom Design

Learn How to Do Mixed-Signal Design at CDNLive! Silicon Valley

With the theme of Connect, Share and Inspire, this year's CDNLive! Silicon Valley…

• 2 min read
real number modeling , APS , Low Power , mixed signal design , CDNLive SV 2012 , parasitic , IC 6.1 , AMS Designer , CPF , analog , Mixed-Signal , analog behavoral , Virtuoso , RNM , CDNLive! , mixed signal , simulation , verification

RF Engineering

Guidelines for Maximizing Speed vs. Accuracy in SpectreRF simulations - Part 3

Several months ago, I started a 3 part series on Guidelines for Maximizing Speed…

• 4 min read
RF , RF Simulation , analog/RF , Circuit simulation , RFIC , QPSS Analysis , shooting newton , HB , Spectre RF , spectre spectreRF , Analog Simulation , MMSIM , RF spectre spectreRF , harmonic trimming , spectreRF , RF design , harmonic balance , mixer

System, PCB, & Package Design 

What's Good About Allegro PCB Router Staggered Via Rules? See for yourself in 16

Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered…

• 1 min read
PCB , PCB Layout and routing , global route , Routing , staggered vias , Allegro 16.5 , via rules , PCB Editor , Layout , vias , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Verification

Differentiation Through Hardware is Not Going Away

Last week at DVCon there was a panel discussion called "The Resurgence of Chip Design…

• 5 min read
High-Level Synthesis , 4G , TLM , hardware , android , system realization , hardware-dependent software , SoC , sub-systems , Quad-HD , iOS , software , DVcon , SystemC , smartphones , tablets

Digital Design

Five-Minute Tutorial: Where To Find More Encounter Digital Implementation (EDI) System…

We've had some people joining the forum lately that are either brand-new to Encounter…

• 1 min read
video , tutorial , beginner , training , EDI 10.1 , Digital Implementation , init_design , five minute tutorial , EDI 11 , mmmc

System, PCB, & Package Design 

What's Good About Allegro DFM/DRC Updates? 16.5 Has a Few New Enhancements!

Allegro PCB Editor has been enhanced in the 16.5 release with three (3) additional…

• 3 min read
PCB , PCB Layout and routing , DFA , backdrill , DRC , ADRC , Allegro 16.5 , SPB , PCB Editor , Layout , assembly DRCs , backdriling , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , Allegro

Analog/Custom Design

Virtuoso AMS Designer Wins the China ACE Best EDA Product Award

The China Annual Creativity in Electronics (ACE) Awards was established to recognize…

• less than a min read
AMS , Virtuoso-AMS , China , mixed signal design , ACE award , AMS-Designer , AMS Designer , Mixed-Signal , wreal

Digital Design

Five-Minute Tutorial: Default Naming Conventions in Encounter Digital Implementation…

This is a topic that frequently comes up on both internal and external forums. And…

• 2 min read
EDI , naming , timing debug , tutorial , encounter , Digital Implementation , Encounter Digital Implementation , default naming conventions , five-minute

System, PCB, & Package Design 

Altera 28 Gbps Stratix V IBIS-AMI Models Now Blazing Channels with Allegro PCB S…

Altera and Cadence recently collaborated and completed correlation work with Allegro…

• 2 min read
PCB SI , PCB , Stratix V , Multi-Gigabit , Altera , IBIS , model kit , PCB power integrity , FPGAs , IBIS-AMI , Signal Integrity , PCB design , channel analysis , SI analysis and modeling , FPGA , Allegro

Verification

Virtual Divide and Conquer Enables Fixed Sub-Systems

The 17th North American SystemC User Group meeting ( NASCUG ), will take place this…

• 3 min read
IP , zynq , virtual platforms , TLM , platform , virtual prototypes , fixed sub-systems , sub-systems , Tensilica , subsystems , OMAP , DVcon , SystemC , xilinx , NASCUG , FPGA , System Design and Verification , verification

Verification

Gentlemen, Start Your Simulation Engines

As we outlined in our recent performance white paper , every verification team has…

• less than a min read
performance , SystemVerilog , Multi-Core , Incisive , Funcional Verification , Incisive Enterprise Simulator (IES) , IES , IES-XL

System, PCB, & Package Design 

What’s Good about OrCAD Apps? Symbol and Footprint Creation Just Got a Lot Easier…

Creating the symbols and footprints necessary to complete your designs can be a difficult…

• 2 min read
PCB , Marketplace , OrCAD Capture Marketplace , Footprint , OrCAD Capture , Capture CIS , Capture-CIS , OrCAD online store , Library flow , Allegro 16.5 , Library and design data management , SPB , webinar , symbol , OrCADapps , "PCB design" , OrCAD , PCB design , Design Entry , SPB16.5 , Librarians , library , PCB Capture , Schematic , Allegro

System, PCB, & Package Design 

What's Good About Capture’s Placement Report? Look to SPB16.5 and See!

The 16.5 release of OrCAD Capture includes the ability to generate a report with…

• less than a min read
"capture CIS" , Allegro Design Entry , hierarchy , Design Entry CIS , flat schematics , Capture CIS , Capture-CIS , property , hierarchical schematics , Allegro 16.5 , SPB , placement report , design , OrCAD , 16.5 , Design Entry , SPB16.5 , PCB Capture , Schematic , Allegro

Verification

Using a Linaro File System on the Cadence Virtual Platform for the Xilinx Zynq-7000…

Linaro has emerged as a great place to find well tested toolchains, Linux kernels…

• 3 min read

Verification

DVCon 2012 Preview: Focus on Formal & ABV Events and Papers

In a few short weeks DVCon 2012 will be upon us ( Feb. 27 - March 1 in San Jose …

• 2 min read
Joe Hupcey III , ABV , verification strategy , Functional Verification , Formal Analysis , ABVIP , Bin Ju , video , tutorial , Facebook , Chris Komar , DVcon , apps , assertion synthesis , assertions , robot , IEV , Assertion-Driven Simulation , Darrow Chu , Formal verification , IFV , Assertion-based verification

System, PCB, & Package Design 

What's Good About ADW’s Server Metrics? Check out the 16.5 Release and See!

The Allegro Design Workbench (ADW) 16.5 has the capability of providing usage metrics…

• 1 min read
PCB , data management , usage metrics , Allegro Design Workbench , Library flow , server metrics , Team design , Allegro 16.5 , SPB , LRM , design data management , configuration manager , design , Library Revision Manager , PCB design , SPB16.5 , metrics , library , ADW

Analog/Custom Design

SKILL for the Skilled: Introduction to Classes -- Part 5

In the previous SKILL for the Skilled postings, we looked at a pretty good algorithm…

• 4 min read
Team SKILL , programming , Sudoku , object orientation , Virtuoso , Lisp , Custom IC Design , SKILL++ , SKILL

Analog/Custom Design

Things You Didn't Know About Virtuoso: Measurements Across Corners

In Virtuoso IC 6.1.5 ISR6, we released a new feature in ADE XL, which had been requested…

• 1 min read
Corners , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Corners analysis , IC615 , IC 6.1.5 , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design
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