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Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Analog/Custom Design

Things You Didn't Know About Virtuoso: ADE XL--Take This Job and...Run It!

Sometimes these articles just write themselves... Last week, 3 different people asked…

• 3 min read
Analog Simulation , analog , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Simulator Fonts, Models, and More? It's in SPB16.3!

The SPB16.3 release of the Allegro AMS Simulator environment contains a few additional…

• 2 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , SPB , AMS simulation , Design Entry , library

RF Engineering

Measure Twice, Cut Once for Transistor ft

Recently there was an inquiry about the methodology for performing the f t (transition…

• 3 min read
RF , Ft , ADE-L , Analog Simulation , Measuring Transistor ft , transistor , Analysis , ADE , Virtuoso , parametric , sweep

Verification

Why EDA Verification is Like Pro Sports

First, I would like to introduce myself. My name is Jim Kjellsen. I've recently joined…

• 2 min read
Functional Verification , football , pro sports , sports , Kjellsen , verification

SoC and IP

Renesas introduces new 1.1Gbit low-latency DDR DRAM (LLDRAM) for networking apps

Renesas has introduced a new 1.1Gbit, low-latency DDR DRAM (LLDRAM) primarily for…

• 1 min read

Verification

Tech Tip: Distributing Incisive Enterprise Verifier (IEV) Engines and Assertions…

A common problem when distributing engines and assertions in Incisive Enterprise…

• 1 min read
ABV , Functional Verification , Formal Analysis , formal , LSF , Enterprise Manager , IEV

SoC and IP

OCZ invents proprietary 20Gbps link for SSDs, snubbing SAS, SATA, and PCIe

Yesterday, OCZ released a curious statement saying that it was unveiling a proprietary…

• less than a min read

SoC and IP

Elpida announces 30nm, low-voltage, low-power, 2Gbit DDR3 SDRAM with TSV (through…

The headline pretty much says it all. Memory vendor Elpida hit all the DRAM high…

• 1 min read

Verification

A Quick Check on the Status of UVM 1.0

Regular readers know that I've blogged a lot about the Open Verification Methodology…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

SoC and IP

LSI Corp to host IC innovation conference and technology showcase in Milpitas next…

On October 5 through 7, LSI Corp will be hosting a conference and technology showcase…

• 1 min read

Verification

Will Your Next System Project Succeed?

Will you have the System Realization tools you need? Will you know how to apply them…

• 3 min read
TLM , webinars , system realization , TSMC , services , ARM , ESL , System Design and Verification

System, PCB, & Package Design 

What's Good About PCB SI DML Path Setting? See For Yourself in the SPB16.3 Release

With the SPB16.3 release of Allegro PCB SI , there’s a new methodology for Device…

• 4 min read
PCB SI , PCB , SI , SPB16.3 , SiP , Signal Intregrity , Digital SiP design , IBIS , SigXP UI , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , IBIS-AMI , SigWave , PCB Editor , design , PCB design , SI analysis and modeling , dml

Digital Design

Guest Blog: Using dbTransform to Translate Geometric Coordinates in Encounter

This is a guest post from JasonG at Avago. I hope you enjoy this useful piece he…

• 4 min read
Avago , dbTransform , encounter , db access , Digital Implementation , tcl

SoC and IP

New Blog: EDA360 Insider, for anyone involved with any aspect of system design

I’ve just started a new blog called the EDA360 Insider ( http://eda360insider.wordpress…

• less than a min read

SoC and IP

Samsung rolls 8Gbyte DDR3 SODIMM, Dell picks it up immediately, stuffs four into…

Samsung has announced that it is now shipping 8Gbyte DDR3 SODIMM SDRAM modules for…

• less than a min read

Verification

Video: Report From The Front Lines Of The Silicon Valley Electronics Industry With…

Lately the tone of the trade press and blogs about the Silicon Valley electronics…

• less than a min read
uvm , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Chu , verification

Analog/Custom Design

Now Playing: Custom IC Videos-to-Go

I wanted to take a brief detour from my usual postings to point out a couple of new…

• 3 min read
IC 6.1 , analog , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

SoC and IP

DRAMeXchange ranks NAND Flash vendors for Q210. Samsung wins, again.

Last month, DRAMeXchange published rankings for the top “branded” NAND Flash vendors…

• 1 min read

Digital Design

Encounter Puzzler #2 Solution: Finding Registers Beneath a Hierarchy

Thanks to everyone who participated in this week's Encounter Puzzer . If you didn…

• 6 min read
dbGet , encounter , Digital Implementation , puzzler , tcl
CDNS - Fix Layout Hompage