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Corporate News

Cadence Recognized as TSMC OIP Partner of the Year at 2025 OIP Ecosystem Forum

The semiconductor industry thrives on collaboration, and few pairings exemplify this…

Corporate
• 2 min read
featured , cadence , OIP Partner of the Year , AI-Driven Design , TSMC

Cadence Japan

境界を越えて、未来を組み上げろ―ホンダ×ケイデンス

「AIは、物理世界にどう根付いていくのか？」をテーマに、本田技術研究所社 先進技術研究所（HGRX）との対談を通じて、AIと半導体の未来、フィジカルAIの可能性…

Cadence Japan
• less than a min read
Automotive , featured , physical ai , automotive electronics , japanese blog

SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI
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Blog - Post List

Latest blogs

Breakfast Bytes

1984 Was Published 70 Years Ago

If you work in any aspect of tech, one book that you have to have read is George…

• 4 min read
george orwell , 1984

Academic Network

Cadence Academic Network Expands to Kazakhstan

Dear reader, may I ask you, what do you know about Kazakhstan ? Do you know that…

• 2 min read
university , Cadence Academic Network , Kazakhstan

Breakfast Bytes

DAC Wednesday: Verification Lunch, Books, and Bagpipes

For my coverage of the first two days of DAC, see my posts DAC Monday: Gaming, IoT…

• 10 min read
DAC , 56dac , Design Automation Conference

Breakfast Bytes

DAC Tuesday: Thomas Dolby, the View from Wall Street, AI Lunch, Denali

It was the second day of DAC yesterday. If you were here, you probably saw some of…

• 6 min read
DAC , 56dac , Design Automation Conference

Whiteboard Wednesdays

Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM…

In this week’s Whiteboard Wednesdays video, Amol Borkar continues his discussion…

• less than a min read
Whiteboard Wednesdays , Vision Q7 DSP , SLAM

System, PCB, & Package Design 

IC Packagers: The (Copper) Pillars of Modern Design

Wire bonding has been around forever. Flip-chip mounting? That’s been around for…

• 7 min read
IC Packaging , IC Packaging and SiP , SiP Layout

System, PCB, & Package Design 

BoardSurfers: Easier Design Work Through Colors, Patterns, and Visibility

PCB and IC Package substrates these days are complex. Multiple layers, hundreds to…

• 4 min read
APD , PCB Editor , PCB design , SiP Layout

Breakfast Bytes

DAC Monday: Gaming, IoT Security, State of EDA Industry, Mixed-Signal Lunch, Cooley…

The Design Automation Conference is in Las Vegas this year. If you are here and want…

• 11 min read
DAC , 56dac , Design Automation Conference

Academic Network

How to Show You’re a Verification Engineer?

There is always a need for verification engineers in the microelectronics industry…

• 1 min read
Specman , Cadence Academic Network , verification

System, PCB, & Package Design 

IC Packagers: Dealing with Large Forms in Low Resolution Screens

Our packages and boards are becoming complex and so are the design tasks we perform…

• less than a min read
IC Packaging and SiP , Allegro Package Designer

Digital Design

Need Help with Liberate Commands and Parameters?

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you…

• 1 min read
parameter , Liberate AMS , liberate blog , liberate trio , Liberate LV , Commands , Liberate Variety , Liberate MX , Cadence Help , Digital Implementation , Liberate , Liberty

Breakfast Bytes

Spectre X: Same Accuracy, New Speed

This morning at DAC, Cadence announced the Spectre X Simulator, the latest version…

• 2 min read
Circuit simulation , Spectre , cadence cloud , spectre x

Breakfast Bytes

Sunday Brunch Video for 2nd June 2019

https://youtu.be/T2VZUEW1ucc Made at Protium Hardware Lab (camera Sean) Monday:…

• less than a min read
sunday brunch

PCB、IC封装：设计与仿真分析

SI工程师如何分析多千兆位串行链路、内存及接口

作者：Ken Willis 早在2007年，Cadence推动了对IBIS标准的扩展，即算法模型接口（AMI），可以模拟多千兆位串行链路接口。这与通道（与传统电路相对…

• less than a min read
SI , Chinese blog , ddr5 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , 信号完整性 , SI分析与建模

Life at Cadence

Appreciating Our Employees

Recognizing the Outstanding Effort that Makes Cadence Successful Cadence hires the…

• 1 min read
awards

Breakfast Bytes

ESD Alliance CEO Outlook: The Leading Edge, Chiplets, Design Costs, Security, and…

The ESD Alliance (and, before that, its forerunner EDAC) runs a CEO Outlook panel…

• 10 min read
ceo outlook , esd alliance

Verification

Got IP Security Questions? This Luncheon at DAC Has Answers

If you’ve got security on the mind—and in this day and age, who doesn’t?—and you…

• 2 min read
security , DAC , luncheon , DAC 2019 , Accellera

Breakfast Bytes

Embedded Vision: Seeing Round Corners, and Reasoning on Microcontrollers

May is a month that seems to have many things associated with it. "Sell in May and…

• 10 min read
deep learning , Embedded Vision Summit , google , mit media lab , neural network

Verification

DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety…

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week…

• 5 min read
security , 5G , DAC , DAC2019 , prototyping , palladium z1 , Safety , tortuga logic , Protium , Emulation , ARM , AI
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