Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P

Cadence Japan

業界初、エッジAI・AI搭載PC向けeUSB2V2エンドツーエンドデモをCESで公開

CES 2026で業界初のeUSB2V2エンドツーエンドデモを公開。AI PCやエッジAI向けの省電力・高速伝送を実現する最新USB技術の詳細をご紹介します。

Cadence Japan
• less than a min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Corporate News

How Cadence Is Energizing Sustainable Semiconductor Design

The demand for semiconductors is surging due to AI growth, data centers, and digital…

• 2 min read
featured , imec , sustainability , energy , semiconductors

SoC and IP

Enhancing Edge AI with the Newest Class of Processor: Tensilica NeuroEdge 130 AI

Artificial intelligence is rapidly expanding its reach into embedded systems and…

• 3 min read
DSP , IP , IoT , Tensilica DSPs , ip cores , Tensilica , semiconductor IP , AI

Corporate News

Ascendance – Decarbonizing Air Transport

Air travel accounts for nearly 3% of global CO2 emissions, and with the increasing…

• 2 min read
CFD , designed with cadence , Fidelity CFD

Life at Cadence

Inspired to Aspire: Great Place to Work’s For All Summit 2025

Glitz, glam, and the afterglow of the world's greatest places to work. The empowering…

• 5 min read
great place to work , life at cadence

Analog/Custom Design

Did You Miss the Boost Your Layout Productivity with Virtuoso Studio Webinar? No…

If you missed joining or registering for the Boost Your Layout Productivity with…

• 1 min read

Life at Cadence

Cadence Women Conference in the Asia-Pacific and Japan Region – A Recap

Written by the APJ CWC Core Team. After several successful Cadence Women Conferences…

• 2 min read
CWC , WomenAtCadence , LifeAtCadence

System, PCB, & Package Design 

UCIe Full SI Analysis Flow with Compliance Check for Heterogeneous Integration

3D heterogeneous integration (3DHI) technology creates high-performance systems by…

• 2 min read

PCB解析／ICパッケージ解析

2025年4月リリース、Sigrity and Systems Analysis 2024.1 HF2 新機能ハイライト

Sigrity and Systems Analysis (SIGRITY/SYSANLS) 2024.1 HF2リリースが Cadence Downloads…

• 3 min read
Sigrity and Systems Analysis , Celsius Studio , japanese blog , Clarity 3D Solver , PowerSI

Analog/Custom Design

Did You Miss the Quantus Insight Webinar? No Worries, the Recording Is Available…

If you missed joining or registering for the Quantus Insight webinar, the complete…

• 1 min read

Analog/Custom Design

Unlocking the Power of Analog Design Verification with Virtuoso ADE Verifier

In the fast-paced world of analog and mixed-signal design, ensuring that your circuits…

• 3 min read
Analog Design Environment , Cadence blogs , custom/analog , analog , ADE , Virtuoso Analog Design Environment , Cadence training , training bytes , Virtuoso , Spectre , cadenceblogs , Cadence Education Services , Custom IC Design , Custom IC , ADE Verifier

Life at Cadence

UK Interns Community Giving Day

UK Interns Lady Payan Cepeda, Seiba Abdul Rahman, and Hudson Ashmoore, hailing from…

• 2 min read
CadenceCares , Culture , giving back , great place to work , life at cadence , cadence emea

Corporate News

Cadence and AVCC to Advance Physical AI Innovations for Autonomous Vehicles

Cadence has joined the Autonomous Vehicle Computing Consortium (AVCC) , marking a…

• 2 min read
Automotive , IP , featured , physical ai , chiplet , Safety , system on chip , HPC , high-performance computing , ADAS

Corporate News

Chip Design Industry Reaches an AI Inflection Point

The chip design landscape has hit a transformative milestone, one that signals a…

• 5 min read
inflection point , featured , agentic ai , agentic

Corporate News

Cadence Agentic AI Reduces SoC/System Engineering Time by Months

The modern design landscape is evolving rapidly, driven by shrinking design cycles…

• 5 min read
featured , agentic ai , AI

Corporate News

Transforming Chip Design with Agentic AI: Introducing Cadence Cerebrus AI Studio

The industry's first agentic AI, multi-block, multi-user SoC design platform To…

• 4 min read
featured , Cadence Cerebrus , Digital Implementation , AI

Analog/Custom Design

Virtuoso Studio IC23.1 ISR14 Now Available

Virtuoso Studio IC23.1 ISR14 production release is now available for download.

• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso , Custom IC Design , Custom IC , IC design , IC23.1

Verification

UALink: Powering the Future of AI Compute

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification…

• 2 min read
Verification IP , VIP , Ethernet , PCIe , HPC , UALink , AI/ML

SoC and IP

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

• 3 min read
hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

System, PCB, & Package Design 

BoardSurfers: Training Insights: Advanced Design Verification with RAVEL

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed…

• 5 min read
PCB , Allegro X PCB Editor , DRC , ravel , Allegro X Advanced Package Designer , APD , PCB Editor , Allegro Package Designer , PCB design , Constraints , allegro x
CDNS - Fix Layout Hompage