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Corporate News

Industry’s First End-to-End eUSB2V2 Demo for Edge AI and AI PCs at CES

Since their debut in 2023, AI PCs have taken the market by storm. Gartner projects…

Corporate
• 4 min read
news story , eUSB2v2 , Edge AI , Design IP , featured

Cadence Japan

ケイデンス、AI設計向け検証IPポートフォリオを強化する新VIP10種を発表

ケイデンスは、AIベースの設計に最適化された最新インターフェース向けに、10種類の新しい検証IP（Verification IP：VIP）を発表しました。今回発表されたVIPは…

Cadence Japan
• less than a min read
news story , Verification IP , featured

Cadence Japan

ケイデンス、株式会社ベリフォアを迎え検証サービスの革新を加速

ケイデンスはVerifore社を迎えて、半導体設計・検証サービスの革新を加速。高品質なソリューションで国内外の競争力を強化します。

Cadence Japan
• 2 min read
featured , japanese blog

Corporate News

Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for…

Corporate
• 1 min read
news story , Verification IP , featured
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Blog - Post List
Latest blogs

SoC and IP

Why is it so difficult to interface with DRAMs?

One of the maxims in the world of system design is that it has always been relatively…

• 3 min read

Verification

The Future of OVM, VMM, and UVM

In my last blog , I took a look back at the history of how we got to the first delivery…

• 3 min read
SystemVerilog , uvm , methodology , Functional Verification , Open Verification Methodology , OVM , VIP , Accellera , Accellera VIP TSC , VMM

SoC and IP

Google TV and Intel’s CE4100 SOC (Sodaville)--is this a world-beating combo or what…

Having vacuumed up most of the world’s very large and growing Internet advertising…

• 5 min read

SoC and IP

MemCon 2010, July 28: Time to Register. Hundreds already have!

How’s your July shaping up? No, that’s not just an idle question about your future…

• 1 min read

Verification

Tech TIP: Incisive Formal GUI Updates - Making It Easier

The Incisive Formal GUI has had some recent changes made to it. You asked for the…

• less than a min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

SoC and IP

Seagate Tweet unleashes avalanche of speculation: fast gamers' 2.5-inch HDD with…

Earlier this week, Seagate sent out the following Tweet: “Your hard drive is…

• 1 min read

System, PCB, & Package Design 

Favorite Features Of An IC Package Designer: Rich And Diverse Set Of Import And Export…

This is the second in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , SiP , Analog and RF SiP design , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , IC Packaging & SiP design , SPB , wirebond profile library , IC Package Physical layout and co-design , Kulicke & Soffa

SoC and IP

LPDDR2: The new mainstream memory for embedded and mobile applications?

Yesterday, ST-Ericsson announced a new smartphone platform called the U8500 which…

• 3 min read

RF Engineering

New Time-Saving Feature in IC6.1.4 ISR2: Plot S-Parameter Data Directly From ViVA…

If you haven't heard about it....there is a new feature in IC6.1.4 ISR2 which makes…

• 2 min read
RFIC , Virtuoso Spectre , Spectre RF , ADE-L , RF designer , MMSIM , Spectre , ViVA , RF design , Circuit Design , harmonic balance , pss

System, PCB, & Package Design 

What's Good About ADW Part Lifecycle? Numerous Improvements in the SPB16.3 Release

The SPB16.3 release of Allegro Design Workbench (ADW) now adds several new key features…

• 1 min read
Allegro Design Workbench , Library flow , Library and design data management , PCB design , ADW 16.3 , Librarians , ADW

SoC and IP

Party on at DAC, says Denali

Back by popular demand, the Denali DAC party. The big one. With the bells and whistles…

• 1 min read

RF Engineering

Using RF Simulation Technology for Analog Applications

The particular nature of analog circuits puts restrictive requirements on circuit…

• 1 min read
RF Simulation , Analog Simulation , RF design , Analog Smart

Verification

UVM World Community Site Now Available!

Yesterday morning, the verification world was buzzing with the first release of the…

• 1 min read
uvm , Verification methodology , Functional Verification , OVM , VIP , Accellera VIP TSC

SoC and IP

1.8-inch SSD with PATA interface targets mini Notebooks, Netbooks, good for embedded…

With all of the recent SSD announcements, you might think that the only form factor…

• less than a min read

Verification

UVM - 10 Years in the Making ...

In case you the missed the news today, the Accellera VIP TSC released the first version…

• 3 min read
SystemVerilog , uvm , Specman , OVM ML , Functional Verification , OVM , OVM e , Coverage-Driven Verification , CDV , vr_ad , OVM SV , e , OVM-e , Accellera , coverage driven verification (CDV) , eRM , Accellera VIP TSC , OVMWorld

SoC and IP

Toshiba stands on 2Xnm NAND platform with devices, SSDs, and hybrid storage

Last week, Toshiba’s president and CEO Norio Sasaki stood firmly upon a leading-edge…

• less than a min read

Verification

Initial Release of the UVM Now Available!

As Richard Goering just reported , the Accellera VIP Technical Subcommittee (TSC…

• 2 min read
uvm , Verification methodology , OVM , VIP , Accellera VIP TSC

System, PCB, & Package Design 

DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

Last year, TimingDesigner improved the interface to PCB SI and many of our joint…

• less than a min read
PCB SI , SI , Signal Intregrity , IBIS , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , "PCB design" , DDR3

SoC and IP

Early Adopter release of UVM now available

Accellera has been working on a new industry-standard verification methodology called…

• 1 min read
CDNS - Fix Layout Hompage