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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Academic Network

Make a DATE with the Young People Programme

Building on the success of previous years, the 2024 edition of the DATE (Design,…

• 3 min read
DATE , Career Fair , GPT Design Contest , Academic Network , PhD Forum , Young People Programme

Digital Design

Training Insights: Cadence Cerebrus Webinar Recording Now Available!

Semiconductor chips must be designed faster, smaller, and smarter—with less manual…

FormerMember • 1 min read

PCB、IC封装：设计与仿真分析

什么是网格划分或网格生成？

庞杂的几何文件、复杂的几何结构，使得 CFD 仿真在网格制作上极其耗时。如何解放工程师的双手， 把更多的精力投入到结果分析和创新性能设计上？本文简述了网格划分的基本概念…

• less than a min read
网格划分 , CFD , Chinese blog , 计算流体力学 , CFD应用 , Fidelity Automesh , 中文 , 汽车 , 流体求解器 , Fidelity Pointwise

Digital Design

Training Insights Webinar: IR-Aware ECO Optimization Using Voltus and Tempus

This training webinar lets you investigate the IR-drop impact on timing and walked…

• 2 min read
ECO , Voltus IC Power Integrity Solution , Cadence training , Digital Implementation , Power Analysis , Tempus Timing Signoff Solution , IR drop , cadence learning and support

データセンター

DataCenter Designソフトウェアを用いたデータセンターの性能検証

ケイデンスのDataCenter Designソフトウェアを用いたデータセンターの性能検証について、ご紹介しています。オンデマンド配信「CadenceLIVE India…

• less than a min read
CFD , ASHRAE compliance , data center , データセンター , DataCenter Design Software , japanese blog

Computational Fluid Dynamics

System-Level Optimization: Why It’s Time to Think Beyond the Silicon

Optimizing a silicon chip at the system level is crucial in achieving peak performance…

• 4 min read
CFD , artificial intelligence , Aerospace , optimization , Aerospace Engineering , AI , simulation

Artificial Intelligence (AI)

The Evolution of Generative AI up to the Model-Driven Era

Generative AI has become a buzzword in 2023 with the explosive proliferation of ChatGPT…

• 6 min read
artificial intelligence , featured , LLM , Generative AI , GenAI

Verification

Building Verification Infrastructure for Complex PCIe Verification

Introduction PCIe (Peripheral Component Interconnect Express) is a high-speed serial…

• 4 min read
Verification IP , Functional Verification , PCIe , pcie gen6

Corporate News

The Power of Computational Software in Biotechnology

As a titan in creating technological solutions for electronic systems design, Cadence…

• 4 min read
featured , biosimulation , openeye , biotechnology

System, PCB, & Package Design 

Cadence Doc Assistant at Your Service

The OrCAD X and Allegro X 23.1 release comes with a brand-new content delivery application…

• 4 min read
documentation , Search , help , Cadence Help , OrCAD X , 23.1 , online documentation , allegro x , Doc Assistant

PCB、IC封装：设计与仿真分析

释放 AI 大模型潜能，硬件算力亟待突破互连瓶颈

完全可以预期，在 OpenAI 明星效应下，全球科技巨头未来一两年必将推出一系列类 GPT 预训练大模型，也有望带动对数据中心 AI 算力集群的投资进一步加速。随着…

• 1 min read
SI , Allegro X AI , Chinese blog , PCB设计 , 中文 , 112g , SerDes , Allegro X 23.1 , 信号完整性 , AI , allegro x

Digital Design

Training Insights – Want to Learn How to Test the Design and Its Need?

Why is Design for Testability (DFT) crucial for VLSI (Very Large Scale Integration…

• 2 min read
digital badge , DFT , Design for Test , training , training bytes , Cadence Modus DFT , online training , Test Automation

PCB、IC封装：设计与仿真分析

详解高密 PCB 走线布线的垂直导电结构 (VeCS)

本文要点：• 什么是垂直导电结构 (Vertical Conductive Structures, VeCS)及其工作原理。• 利用 VeCS 进行 PCB 设计的优势…

• 1 min read
Chinese blog , PCB设计 , Layout , 中文 , Allegro X 23.1 , 布局布线 , 垂直导电结构 , allegro x

Spotlight Taiwan

Cadence Awarded MOEA’s 2023 International Partner Office Award

Cadence is awarded a second time for driving the development of the Taiwan semiconductor…

• 2 min read
Taiwan , taiwanese blog , intelligent system design

Data Center

The Importance of Pre-Configured Library Items when Modeling Data Centers

No one wants to waste unnecessary time in the model creation phase when using a modeling…

• 5 min read
data center , thermal

Corporate News

The Top Secret Engineering Team at Cadence

The Silicon Engineering Team – Mission Impossible Superstars In the fast-paced world…

• 4 min read
featured , services , ARM

Analog/Custom Design

Start Your Engines: Best Practices for Converting a Logic Signal to Electrical Value…

You can easily convert a logic signal to an electrical value using the Verilog-AMS…

• 7 min read
AMS , AMS Designer , mixed signal solution , analog/mixed-signal , AMS simulation , mixed-signal design , AMS Verification , mixed-signal verification

Verification

Navigating Cache Coherence: The Back-Invalidate Feature in CXL 3.0

In the rapidly evolving landscape of data centers, ensuring cache coherence in multi…

• 2 min read
CXL , performance , Verification IP , Functional Verification , coherent , HIgh Speed Interconnect

Spotlight Taiwan

Cadence榮獲經濟部頒贈2023電子資訊國際夥伴績優廠商獎(IPO Award)

再度肯定Cadence對提升台灣半導體核心研發能量的卓越貢獻全球電子設計創新領導廠商益華電腦(Cadence Design Systems, Inc.)宣布今年再度榮獲經濟部頒發…

• less than a min read
Taiwan , taiwanese blog , intelligent system design
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