Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

Alberto's Keynote: Cadence and Academia

On the last day of CadenceLIVE 2020, there was a keynote by Alberto Sangiovanni-Vincentelli…

• 4 min read
Berkeley , Alberto Sangiovanni-Vincentelli

定制IC芯片设计

Virtuoso Meets Maxwell: Bumps, Bumps……如何找到Bumps？

Bumps对Virtuoso MultiTech Framework解决方案来说至关重要, 它提供了堆叠芯片，中介层，封装和电路板两两间的连接。 Bump的位置…

• less than a min read
Chinese blog , ICADVM18.1 , Edit-in-Concert , Co-Design , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , stacked devices , stacked solution , bumps

Breakfast Bytes

Sunday Brunch Video for 16th August 2020

https://youtu.be/7W55PNo-SoI Made in "CadenceLIVE Lounge" (camera me) Monday: 120th…

• less than a min read
sunday brunch

Analog/Custom Design

Start Your Engines: Pointers to Speed Up a Slow Mixed-Signal Simulation

There may be times when the mixed-signal verification engineers observe a slow analog…

• 2 min read
mixed signal design , mixed-signal methodology , AMS Designer , analog behavioral models , mixed signal , wreal , real number models , SPICE , AMS Verification , vams , mixed-signal verification

Breakfast Bytes

CadenceLIVE 2020: As It Happened

CadenceLIVE 2020 Americas took place virtually earlier this week, spread across Tuesday…

• 4 min read
Facebook , Lip-Bu Tan , annapurna , aws , datacenter

Analog/Custom Design

Virtuosity: In the Line of Veri-Fire - Episode 4

Want to know what's new in this episode of Veri-Fire? Check it out!

• 6 min read
verifier , Analog Design Environment , Cadence blogs , ICADVM18.1 , custom/analog , Analog Coverage , Rapid Adoption Kit , Analog Simulation , analog , ADE , analog verification , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , cadenceblogs , FAQ , implementations , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , Assembler , Verifier new feature , custom design technology , ADE Assembler , verification

Breakfast Bytes

Computational Logistics

General Omar Bradley famously said: “Amateurs talk strategy. Professionals talk logistics…

• 3 min read
computational logistics , computational software , verification

Academic Network

Custom IC, Analog, and RF Design Training Deep Dive: Part 3

Welcome to part 3 of the Custom IC, Analog, and RF Design Online Training deep dive…

• 4 min read
Europractice , Cadence Academic Network , CMC Microsystems , Virtuoso , online training , SKILL , university program

Breakfast Bytes

Xcelium ML: Black-Belt Verification Engineer in a Tool

What if I told you I knew someone who could improve your regression efficiency: make…

• 4 min read
deep learning , xcelium ml , machine learning , DVcon , xcelium , simulation

Analog/Custom Design

Virtuoso Meets Maxwell: Magic! – Dynamic Voiding in Virtuoso RF Solution

While SiP Layout Option is – and continues to be – one of the most complete solutions…

• 7 min read
ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF Solution , Virtuoso RF , Dynamic Shapes , Dynamic Voiding , Custom IC Design

System, PCB, & Package Design 

BoardSurfers: Allegro In-Design Crosstalk Analysis: Signal Integrity Simulations…

Crosstalk is the transfer of unwanted signals from an “aggressor” net to a “victim…

• 2 min read
PCB design and layout , PCB Signal integrity , Allegro PCB Editor , Allegro

System, PCB, & Package Design 

IC Packagers: Make Acute Angles a Sharp Problem of the Past

Sharp angles, whether they create a spike in a poured shape or form an acid trap…

• 5 min read
Allegro Package Designer , 17.4-2019

Breakfast Bytes

Cadence Executives on Computational Software

CadenceLIVE starts today, Tuesday, August 11, and runs through Thursday. One thing…

• 3 min read
computational software , cadencelive

カスタムIC／ミックスシグナル

Virtuosity: Multi-Technology Simulation (MTS)の実行方法は？

マルチ・テクノロジ・シミュレーション(Multi-Technology Simulation; MTS)を Virtuoso® ADE Explorer と Virtuoso…

• less than a min read
Explorer , Rapid Adoption Kit , Virtuoso , Spectre , ADE-XL , Virtuosity , japanese blog , Custom IC Design , Assembler , ADE Assembler

Digital Design

Voltus Voice: Demystifying ESD – Touch Ground with a Designer-Centric Protection…

This blog highlights the key capabilities and benefits of the Voltus ESD analysis…

• 5 min read
effective resistance , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , electrostatic discharge , current density , Power Integrity , Innovus , Charged Device Model , Full-Chip , ESD

Breakfast Bytes

120th Anniversary of Hilbert's Problems

The computational software algorithms used in EDA are fundamentally mathematical…

• 3 min read
hilbert's problems , computational software , millennium prize problems

PCB、IC封装：设计与仿真分析

电子系统设计中进行片上热分析的四大挑战与应对

在大约 138 亿年前的创生之初，我们的宇宙在 0 到 10-43 (10^(-43))秒的短短时间里产生和释放了大量的热量或能量，这在理论上得到了各种模型和测量数据的支持…

• less than a min read
Celsius Thermal Solver , 热 , PI , Chinese blog , 电源完整性 , 热分析 , 3D 分析 , EE Thermal , 电热协同仿真 , 热传输 , Voltus , 中文 , 系统分析 , IC封装 , 异质封装

Breakfast Bytes

Weekend Update 2

This is my second update post where I cover things that I have covered before, and…

• 2 min read

Breakfast Bytes

Rigid-Flex

Rigid-flex sounds like something that might be a Crossfit workout-of-the-day. But…

• 5 min read
PCB , Rigid-Flex , Allegro
CDNS - Fix Layout Hompage