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Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

BoardSurfers: Everything You Need to Know About Fixed Fillets/Teardrops

First, teardrops and fillets are interchangeable words in PCB design, and both terms…

• 4 min read
Allegro Package Designer , Allegro PCB Editor

System, PCB, & Package Design 

IC Packagers: Staggering Shape Outlines

Having coincident edges shared across multiple layers is frequently not a desirable…

• 4 min read
IC Packaging , PCB Editor , Allegro Package Designer , 17.4-2019 , Allegro

Digital Design

Voltus Voice: Power Signoff Ramp-Up RAKs – Hello Electrical, Meet Thermal!

This blog introduces the Voltus-Celsius Electro-Thermal Analysis RAK that will give…

• 4 min read
Celsius Thermal Solver , Silicon Signoff and Verification , electromigration , Voltus IC Power Integrity Solution , Power Signoff , Multi-Physics Technology , 3D-IC , Power Integrity , co-simulation , electrical-thermal , Thermal Analysis , design closure , IR drop , RAKs

Analog/Custom Design

Start Your Engines: Seamlessly Reusing Advanced Digital Testbenches in AMS UNL

The Virtuoso Advanced Testbench Reuse flow with Xcelium eases the painful process…

• 2 min read
SystemVerilog , AMS , uvm , Functional Verification , mixed signal methodology , AMS Designer , Mixed Signal Verification , Unified Netlister , SV-RNM , SVA , analog/mixed-signal , assertions , mixed signal , mixed-signal design , MDV , AMS Verification , mixed-signal verification , verification

Analog/Custom Design

Virtuoso Meets Maxwell: Cross-Fabric Electromagnetic Extraction - Eliminating the…

With modules coming from multiple platforms, cross-fabric EM analysis becomes an…

• 8 min read
Virtuoso ICADVM18.1 , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Electromagnetic analysis , Virtuoso , Custom IC Design , Virtuoso Layout Suite

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 技巧五：布线技巧

布线阶段如何减少重复性机械劳动？让工具处于最佳使用状态，为您赢得设计思考和规划的时间。 布线设计并非连连看，熟悉布线设置、实现成组布线，都能使布线工作事半功倍，从而交付高质量的PCB设计作品…

• 1 min read
Chinese blog , 软件技巧 , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro PCB Designer , Allegro , 专家培训

PCB、IC封装：设计与仿真分析

极致PCB设计全流程 I 基础五：布线规划

布线阶段如何减少重复性机械劳动？让工具处于最佳使用状态，为您赢得设计思考和规划的时间。 布线设计并非连连看，而是设计思路的物理实现，有了设计思路+系统规划，才能交付高质量的PCB设计作品…

• 1 min read
Chinese blog , 软件技巧 , webinar , PCB设计 , 中文 , 直播网课 , online training , Allegro PCB Designer , Allegro , 专家培训

Digital Design

Library Characterization Tidbits: Rewind and Replay - 2

A recap of the blogs published in the Library Characterization Tidbits blog series…

• 2 min read
Liberate AMS , Liberate LV , RAK , Liberate Variety , Application Notes , Library Characterization Tidbit , Liberate , Liberate Characterization Portfolio

Verification

Troubleshooting Xcelium Errors/Warnings with xmhelp/xmbrowse and Cadence Support…

I joined Cadence in July 2000 and was immediately put on a three-month training to…

• 4 min read
extended help , incisive utility nchelp , nchelp , troubleshooting xcelium errors , xcelium error extended help , incisive error extended help , xmhelp

Breakfast Bytes

Celsius and Voltus: 2+2=5

I recently attended a webinar presented by Rajat Chaudhry, who is a Product Engineering…

• 6 min read
celsius , Voltus , thermal

Analog/Custom Design

Virtuosity: In the Line of Veri-Fire - Episode 2

Hi readers! Welcome to Veri-Fire, a blog series that helps you deep dive into Virtuoso…

• 6 min read
verifier , Analog Design Environment , Cadence blogs , ICADVM18.1 , Analog Coverage , verification plan , analog , ADE , analog verification , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , Virtuosity , ADE Blog Series , FAQ , implementations , analog design , Custom IC Design , requirements , Custom IC , ADE Verifier , IC6.1.8 , Assembler , Verifier new feature , custom design technology , ADE Assembler , verification

Breakfast Bytes

Clarity, Sigrity, EMX, and AWR: So Many EM Solvers to Choose From…

Cadence has multiple electromagnetic (EM) technologies within its product portfolio…

• 6 min read
RF , AXIEM , Virtuoso RF , EMX , Sigrity , EM , clarity

Academic Network

Great Collaboration on Teaching Verification with Bosch Sensortec and HTW Dresde…

The HTW Dresden - University of Applied Sciences offers several courses in the area…

• 3 min read
HTW Dresden , Specman , Cadence Academic Network , Bosch Sensortec , verification

Breakfast Bytes

Analyzing On-Chip RF Passives

RF stands for radio-frequency. Obviously, this covers radios of all types, but as…

• 7 min read
RF , EMX , RF design , radio

Digital Design

iSpatial Flow in Genus: A Modern Approach for Physical Synthesis

With advanced-process nodes, the physical delay of a standard cell, net delay, and…

• less than a min read
Genus , video , Logic Design , physical implementation

System, PCB, & Package Design 

BoardSurfers: Training Insights: Adding and Re-Ordering Mask Layers

One idea that completely revolutionized the concept of PCB making is adding layers…

• 3 min read
17.4 , 17.4-2019 , PCB design , Allegro PCB Editor

System, PCB, & Package Design 

IC Packagers: Renaming Nets in a Layout

As the component count increases in package/interposer designs, many more of you…

• 4 min read
17.4 , IC Packaging , Allegro Package Designer , 17.4-2019

Breakfast Bytes

Zhuo Li, DAC Chair, Plus Cadence@DAC

Yesterday was my DAC Preview post. As it happens, Cadence's Zhuo Li is this year…

• 4 min read
57dac , DAC , Accellera , Design Automation Conference

カスタムIC／ミックスシグナル

Virtuosity: 洗練されたExtractedビュー

Cadence® Quantus Smart Viewは、Virtuoso環境の次世代のExtracted Viewです。Smart Viewは、Extracted…

• 1 min read
Smart View , PAD , ICADVM18.1 , ADE Explorer , Virtuoso , Parastics , Virtuosity , japanese blog , Quantus , IC6.1.8 , ADE Assembler , Virtuoso Layout Suite XL
CDNS - Fix Layout Hompage