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Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
Corporate 30 Jun 2026 • 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

  • All 6439
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  • Artificial Intelligence 28
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  • Computational Fluid Dynamics 375
  • Data Center 60
  • Digital Design 465
  • Learning and Support 63
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1018
  • Verification 1332
  • Cadence Japan 18
  • Physical Systems Simulation 25

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Academic Network

Cadence Academic Network Presents at Khalifa Semiconductor Research Center

On Nov. 18 Dr. Patrick Haspel presented at Khalifa Semiconductor Research Center…

Anton Klotz 8 Dec 2015 • 1 min read
Cadence Academic Network , UAE , Khalifa

Academic Network

Using Constraints Generation When Designing Power-Constrained SoCs

If you’re designing SoCs, power is no doubt one of your top concerns—power scheduling…

Christine Young 8 Dec 2015 • 3 min read
constraints generation , Professor Farid Najm , power constrained SoCs , power grid , Power Integrity , voltage drop , power scheduling

Breakfast Bytes

Rob Aitken of ARM Research on System Design

I wrote yesterday of how there is a transition going on as system companies discover…

Paul McLellan 8 Dec 2015 • 2 min read
SDE , system design , Rob Aitken , system design enablement , ARM , Breakfast Bytes

Academic Network

Why Agile Software Methodologies Can Improve the Chip Design Process

UC Berkeley Professor Borivoje Nikolic sees agile software methodologies as an answer…

Christine Young 7 Dec 2015 • 3 min read
Berkeley engineering , AMS , agile software development , open source , mixed signal , UC Berkeley

Academic Network

Cadence Tech Days at ITMO and MIET

Cadence Academic Network organizes TechDays in Russia to promote leading-edge technologies…

Anton Klotz 7 Dec 2015 • 1 min read
MIET , Cadence Academic Network , Russia , ITMO

Breakfast Bytes

Applications Down to Transistors: System Design Enablement

Last year Dan Nenni and I wrote a book on the semiconductor industry through the…

Paul McLellan 7 Dec 2015 • 5 min read
SDE , fabless , moore's law , system design enablement , Breakfast Bytes , foundry

Academic Network

10th Cadence Design Contest 2015 Successfully Organized in India

Cadence India organized the 10th edition of the Cadence University Program’s flagship…

Anton Klotz 6 Dec 2015 • 1 min read
EDA , Cadence Design Contest , India , university program

Academic Network

Xtensa Design Contest 2015 in India

The Cadence® Xtensa® Design Contest is an initiative of the Cadence India University…

Anton Klotz 5 Dec 2015 • less than a min read
Cadence Academic Network , Cadence India , Xtensa Design Contest , university program

Academic Network

Cadence Innovus Implementation System is Available to Academia

To support academia using the latest industry-standard tools, Innovus™ Implementation…

Anton Klotz 4 Dec 2015 • 1 min read
Routing , academia , Innovus , implementation , Placement

Breakfast Bytes

Front-end Design Summit

Wednesday was the annual Front-end Design Summit at Cadence headquarters. This focuses…

Paul McLellan 4 Dec 2015 • 4 min read
Genus , Encounter Test , manufacturing test , Joules , front end design summit , Test , front end design , Synthesis , power , Breakfast Bytes

Academic Network

Cadence Academic Network - The Next Generation

“University students around the world are using Cadence technology to learn and develop…

Anton Klotz 3 Dec 2015 • 2 min read
Cadence interns , Cadence Academic Network , EDA , engineering

System, PCB, & Package Design 

What's Good About PCB Allegro Rules Developer and Checker? 16.6 Has It!

You can now leverage the 16.6-2015 release Allegro Rules Developer and Checker .…

Jerry GenPart 2 Dec 2015 • less than a min read
Constraint-driven PCB Design flow , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , High Speed , PCB Editor , High-Density Interconnect , Layout , PCB design , Allegro PCB Editor , differential pairs

Breakfast Bytes

Why Do Layout Designers Say "Stream Out"?

For the same reason we "hang up" our phones. When a layout designer saves a design…

Paul McLellan 2 Dec 2015 • 6 min read
GDSII , Stream Out , Layout , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays—DUT Verification with Cadence VIP

In this week's Whiteboard Wednesday's video, Arindam Guha explains how to quickly…

References4U 1 Dec 2015 • less than a min read
DUT verification , Verification IP , Whiteboard Wednesdays , VIP

SoC and IP

Will USB Type-C Connector Replace the 3.5mm Audio Jack?

In the past few days, there have been many posts on the Internet around Apple planning…

Jacek Duda 1 Dec 2015 • 1 min read
USB 3.0 , Jacek Duda , USB-IF , USB , power delivery , USB 2.0 , Type-C , Design IP and Verification IP , USB connector , USB 3.1

Breakfast Bytes

Virtuoso: Advance to 10nm, If You Pass Go Collect $200

There are two major discontinuities in the last couple of process nodes—FinFETs and…

Paul McLellan 1 Dec 2015 • 5 min read
EAD , FinFets , iPVS , Custom Routing , multi-patterning , Virtuoso , 10nm , modgens , color-aware layout , Breakfast Bytes

System, PCB, & Package Design 

Take Tighter Control Over Your Shape Degassing Patterns with Cadence 16.6 Allegro…

With metal density and balancing requirements getting stricter with every year that…

ICPackagingPro 30 Nov 2015 • 6 min read
Cadence Design Systems , SiP Design , 16.6 , IC package design , APD , Allegro Package Designer , manufacturing , SiP Layout , shapes

Breakfast Bytes

TSMC 3D. Red and Green Glasses Not Required

I have been taking a look at TSMC's 3D packaging technologies. From numerous presentations…

Paul McLellan 30 Nov 2015 • 4 min read
CoWoS , 3DIC , info-pop , TSMC , InFO , info_s , Breakfast Bytes

Breakfast Bytes

Can You Pass As a Brit? Just Answer 3 Simple Questions

It’s Thankgiving! Happy Thanksgiving if you are reading this on the day. Cadence…

Paul McLellan 26 Nov 2015 • 9 min read
thanksgiving , lbw , guy fawkes , gunpowder plot , glorious revolution , marmite
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