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SoC and IP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

Corporate News

AI Infra Summit Highlights: Cadence's Unique Design for AI and AI for Design

The AI Infra Summit 2025 was a great experience that left attendees buzzing with…

Corporate
• 7 min read
featured , AI Infra Summit 2025 , AI for design , Cadence Reality Digital Twin Platform , design for AI

Corporate News

Ambarella Redefines Edge AI Performance with Cadence

Ambarella stands at the forefront of edge AI processing, pioneering low-power, high…

Corporate
• 4 min read
Edge AI , featured , Ambarella

Corporate News

Explore Photonics and Quantum Technologies at CadenceCONNECT 2025

The intersection of photonics and quantum computing marks a pivotal moment in advancing…

Vinod Khera
• 1 min read
Quantum States , featured , cadenceconnect , photonics , Quantum Technology
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Blog - Post List

Latest blogs

System, PCB, & Package Design 

DDR3 Timing issues? Watch the Allegro PCB SI / TimingDesigner Webinar!

Last year, TimingDesigner improved the interface to PCB SI and many of our joint…

• less than a min read
PCB SI , SI , Signal Intregrity , IBIS , PCB Signal and power integrity , Allegro 16.3 , SPB 16.3 , "PCB design" , DDR3

SoC and IP

Early Adopter release of UVM now available

Accellera has been working on a new industry-standard verification methodology called…

• 1 min read

Verification

EDA360: Cool People Creating Cool Stuff

Now that we have had some time to reflect on the meaning of EDA360 , it occurred…

• 4 min read
EDA360 , Systemm Design and Verification , OpenStreetMap , Embedded Linux , Embedded Software Engineer

Digital Design

What you didn’t know about DFM for advanced node designs: “In-route” is insuffic…

Recently, there has been a lot of buzz about addressing DFM issues during routing…

• 3 min read
Digital Implementation forums , DRC , design rules , EDA , Encounter Digital Implementation System 9.1 , Manufacturability sign-off , Digital Implementation , Encounter Digital Implementation , EDI system Encounter Digital Implementation System , DFM

SoC and IP

SSDs in embedded control: cold rolling steel in old European factories

By far, most application stories connected with SSDs revolve around servers and PCs…

• 3 min read

SoC and IP

CADENCE TO ACQUIRE DENALI

Complementary Transaction Supports Cadence’s EDA360 Vision SAN JOSE and SUNNYVALE…

• 2 min read

System, PCB, & Package Design 

Economic Recovery on the Way to the Airport

Last week, one of the members of TEAMOrCAD took a trip to China. The ride to the…

• 1 min read
"capture CIS" , PSPICE , "PCB design" , OrCAD , PCB Capture , Schematic

SoC and IP

Mass marketing methods come to SSDs

Newly introduced and available for pre-availability orders, the privately branded…

• 3 min read

System, PCB, & Package Design 

What's Good About SCM and Packageable Schematics? The Secret's in the SPB16.3 Release

Many customers want to use System Connectivity Manager (SCM) known as Allegro System…

• 1 min read
SCM , Allegro Design Entry , DEHDL , SPB 16.3 , Design Entry HDL , ASA , Allegro System Architect (ASA) , Front-end PCB design , PCB design , Design Entry , ConceptHDL , Schematic

SoC and IP

Enterprise-class HDDs due to disappear, soon. All hail the enterprise-class SSD.

The great Grand Poobah of SSD research Jim Handy released an industry report on Enterprise…

• 1 min read

SoC and IP

Last call for free DAC tix

The DAC 2010 (DAC47) free exhibit passes program has been a big success with more…

• 1 min read

Verification

Inside Cadence: Training for EDA360

Over the past few weeks all of Cadence's Verification and Systems Solutions Applications…

• 5 min read
Specman , TLM , OVM ML , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , OVM , VIP , OVM e , CtoSilocon , OVM SV , e , Enterprise Manager , Palladium XP , MDV , IEV , Incisive Enterprise Simulator (IES) , IFV , IES-XL

Verification

FMCAD Call for Papers Extended to May 12

Team Verify would like to inform you about the final call for papers for FMCAD 2010…

• 7 min read
ABV , Functional Verification , Formal Analysis , formal , Incisive , IEV , IFV

SoC and IP

SSDs don’t need disk interfaces. Case in point: OCZ’s USB 3.0 SuperSpeed Enyo

Most SSDs are designed to be interface- and form-factor-compatible with existing…

• 1 min read

SoC and IP

New White Paper discusses the challenges of chip design based on AMBA 4

ARM’s series of AMBA specifications have become a de facto standard for SoC (system…

• 2 min read

SoC and IP

Memory Market Outlook for 2010: How Bad (or Good) is it?

If you’ve been following the roller-coaster ride that constitutes the global semiconductor…

• less than a min read

System, PCB, & Package Design 

What's Good About DEHDL Alignment? You’ve got it in the SPB16.3 Release!

Schematic construction requires a lot of effort in placing components, wires and…

• 2 min read
Allegro Design Entry , DEHDL , Allegro 16.3 , SPB 16.3 , Component Alignment , SPB , Design Entry HDL , Front-end PCB design , Design Entry , ConceptHDL , Schematic

Verification

Informative Tweets on WHEN Inheritance

Earlier today a lively and very instructive thread on the relative virtues of WHEN…

• 3 min read
SystemVerilog , when sub-typing , tweeting , Specman , Functional Verification , when inheritance , OVM , OVM e , OVM SV , e , Twitter , AOP , IES-XL

Verification

What Does EDA360 Mean for Verification Engineers?

I trust that most of you have seen the recent flurry of blog posts and articles about…

• 2 min read
uvm , IP , Verification methodology , OVM , VIP , EDA360
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