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Featured

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
Corporate 15 Jun 2026 • 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
Corporate 11 Jun 2026 • 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
Corporate 2 Jun 2026 • 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Artificial Intelligence (AI)

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
Corporate 31 May 2026 • 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design
cdns - all_blogs_categories

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  • System, PCB, & Package Design  1015
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Blog - Post List
Latest blogs

Breakfast Bytes

Sunday Brunch Video for 27th June 2021

https://youtu.be/nD_AYa2AbfU Made in my car (camera: my car's phone mount) Monday…

Paul McLellan 27 Jun 2021 • less than a min read
sunday brunch

Computational Fluid Dynamics

This Week in CFD

It's Friday which means it's time to take a look back at what happened in the CFD…

John Chawner 25 Jun 2021 • less than a min read
CFD , geometry modeling , Pointwise , Computational Fluid Dynamics , CAD , Omnis

Breakfast Bytes

June Update: PCIe 6.0, Ransomware, Mars, Turing Award...and CadenceLIVE

I have decided to put these "Update" posts that I do from time to time on a more…

Paul McLellan 25 Jun 2021 • 4 min read
ransomware , turing award , pcie 6 , PCIe , turing , Mars

Analog/Custom Design

Virtuosity: Mystery Behind the .simrc File and Netlist Customization

Read on to know the usefulness of the .simrc file and how and when it is picked by…

Rashmi G 24 Jun 2021 • 7 min read
ic design methodology , AMS , Analog Design Environment , ic analog design , Cadence blogs , programming , mixed-signal simulators , custom/analog , Analog Simulation , analog , Mixed-Signal , full custom ic design , Virtuoso Analog Design Environment , Virtuoso , Spectre , Virtuosity , cadenceblogs , ICADVM20.1 , Circuit Design , mixed signal , analog design , Custom IC Design , IC6.1.8 , SKILL , Schematic , Analog IC Design , custom design technology , custom integrated circuit

Breakfast Bytes

Quantum Computing with Spectre's Ultra-Low Temperature Models

Equal1 has just announced a breakthrough in quantum computing with a fully integrated…

Paul McLellan 24 Jun 2021 • 6 min read
quantum computing , 22fdx , gf , GlobalFoundries , FD-SOI

PCB、IC封装:设计与仿真分析

动态电压和频率调节如何影响功耗

本文要点 降低 CPU 或 GPU 功耗的技术有许多,这些技术聚焦软件/固件层面、系统层面和晶体管架构层面 其中两种降低功耗的技术为:动态电压和频率调节,即调整电源电平…

Sigrity 23 Jun 2021 • less than a min read
PI , Chinese blog , 电源完整性 , 仿真分析 , GPU , 功耗 , Sigrity X , 中文 , 系统分析 , Sigrity , CPU

System, PCB, & Package Design 

BoardSurfers: Training Insights: A Comprehensive Solution for Setting Up PCB Design…

PCB design complexities increase with the increase in the number of parts and layers…

Niharika1 23 Jun 2021 • 3 min read
17.4 , BoardSurfers , PCB Editor , 17.4-2019 , PCB design , Training Insights , Allegro PCB Editor , Allegro

Breakfast Bytes

New Banknote with Alan Turing: "This Is a Foretaste of What Is to Come, and the Shadow…

Today is Alan Turing's birthday. More to the point, today the first £50 banknotes…

Paul McLellan 23 Jun 2021 • 5 min read
bank of england , bletchley park , computer science , turing

Digital Design

Pegasus: Get your Wings: Pegasus Run Controls

Have you ever been in a situation where the run has started and you realize that…

Sarita Sharma 22 Jun 2021 • 4 min read
Pegasus Verification System , Run Control Commands , pegasus , Pegasus Run Control , signoff

Computational Fluid Dynamics

Overcoming Geometry Model Challenges for CFD Mesh Generation

I have often said that geometry modeling is to mesh generation what turbulence modeling…

John Chawner 22 Jun 2021 • 7 min read
CFD , geometry modeling , Pointwise , Computational Fluid Dynamics , CAD , Mesh Generation , Computer Aided Design

Computational Fluid Dynamics

New Release - Omnis Version 5.1 Is Out Now!

Want to see it in action? VIEW WEBINAR RECORDING The newest version of the…

AnneMarie CFD 22 Jun 2021 • 2 min read
CFD , Computational Fluid Dynamics , Omnis

Breakfast Bytes

Jim Hogan and Ed McCluskey Named Honorees of the Phil Kaufman Hall of Fame

In February of this year, the ESD Alliance and IEEE CEDA announced the creation of…

Paul McLellan 22 Jun 2021 • 4 min read
ieee ceda , Jim Hogan , jed mccluskey , esd alliance

Verification

PIPE SerDes Architecture for PCIe Gen 5 and Beyond

Intel PIPE (PHY Interface for PCIE, SATA, USB3.1, DisplayPort and USB4) specification…

Sangeeta Soni 21 Jun 2021 • 2 min read
Intel , IP verification , PHY , pcie 5 , VIP , PCIe , SerDes , pcie gen6

Computational Fluid Dynamics

This Week in CFD

It's a short week here at Cadence CFD as we celebrate the Juneteenth holiday today…

John Chawner 18 Jun 2021 • less than a min read

PCB、IC封装:设计与仿真分析

Cadence 收购计算流体动力学公司 NUMECA

本文翻译自Cadence “Breakfast Bytes Blogs”专栏作者Paul McLellan文章 “Cadence to Acquire Computational…

SDA China 17 Jun 2021 • less than a min read
CFD , Chinese blog , 计算流体动力学 , 中文 , 系统分析 , NUMECA , 多物理场仿真 , Omnis

Analog/Custom Design

Virtuosity: Bindkeys in Virtuoso Layout Suite

You can use Virtuoso keyboard shortcuts called bindkeys in Virtuoso Layout Suite…

Sucharita 17 Jun 2021 • 3 min read
Virtuoso Layout Bindkeys , Bindkeys in VLS , Virtuoso Keyboard Hotkeys , ICADVM20.1 , Virtuoso Keyboard Shortcuts , Custom IC Design , Virtuoso Layout Suite , IC6.1.8

Breakfast Bytes

The EVS Codec: The Movie

I have written before about standards in general (including one that is 2000 years…

Paul McLellan 17 Jun 2021 • 2 min read

System, PCB, & Package Design 

(P)SpiceITUp: The Power of Options in Managing Accuracy and Speed Using Relative…

The tolerances are not unique to only PSpice or simulators, they are part of any…

mrigashira 17 Jun 2021 • 5 min read
17.4 , OrCAD Capture , PSpiceA/D , logical design , (P)SpiceItUp , PSPICE , 17.4-2019 , OrCAD , simulation

カスタムIC/ミックスシグナル

Spectre Tech Tips: Spectreアナログフォルト解析の紹介

プロセスの微細化に伴い、不具合が発生しやすくなったため、チップテストの要求が厳しくなっています。これらの欠陥はフォルトとしてモデル化され、回路シミュレータに提供されてフォルト解析が行われます…

Custom IC Japan 16 Jun 2021 • less than a min read
onestep , fault analysis , DFA , timezero , opens , bridges , Legato Reliability Solution , maxiters , custom faults , direct fault analysis , spectre_fsrpt , faultleadtime , tfa , Spectre , spectre_ddmrpt , parametric faults , linear , japanese blog , transient fault analysis , detection matrix
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