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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

Breakfast Bytes

It's Ada Lovelace Day Today

The second Tuesday in October is Ada Lovelace Day (ALD). This is not just a day to…

• 6 min read
analytical engine , ada , ada lovelace , Babbage

Analog/Custom Design

Virtuoso Meets Maxwell: Package PDK in Virtuoso! How Is it even possible!? (Part…

You heard it right! Virtuoso now supports Package and Board level designs; therefore…

• 4 min read
SiP , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Layout EXL , Virtuoso Meets Maxwell , Virtuoso RF , Layout EXL , Package Design in Virtuoso , Electromagnetic analysis , Virtuoso , RF design , Custom IC Design , Allegro

Breakfast Bytes

What Is Quantum Supremacy?

There are rumors that Google has achieved quantum supremacy. According to Scott Aaronson…

• 4 min read
quantum computing , IBM , quantum supremacy , google

Breakfast Bytes

Sunday Brunch Video for 6th October 2019

https://youtu.be/zEmNTM72GYE Made at Sawyer Camp Trail (camera Carey Guo) Monday…

• less than a min read
sunday brunch

Academic Network

Student Story: Min-Chun's Contribution to Cell-Aware Test

Let me introduce myself. My name is Min-Chun Hu, a master student majoring in electrical…

• 2 min read
Cadence interns , Interns , Cadence Academic Network , pegasus , modus , imec , Spectre , Quantus

PCB、IC封装：设计与仿真分析

关于PCB设计倒角需要了解的一切

将任意一个角落切掉，便能得到一个倒角。从儿童防护桌到泰姬陵的标志性外墙，人类通过倒角来解决与角相关的功能和美学问题由来已久。 使两个表面以90°以外的角度，尤其是45…

• less than a min read
PCB , Chinese blog , PCB设计 , 中文 , Allegro PCB Editor , Allegro , 倒角

Breakfast Bytes

EDA in the Cloud: Astera Labs, AWS, Arm, and Cadence Report

Earlier this week I wrote a post covering the AWS presentation from HOT CHIPS about…

• 6 min read
cloud , aws , cadence cloud , Liberate , Amazon

Analog/Custom Design

Virtuoso Video Diary: Multi-Technology Simulation—The Good has Changed for Bette…

This blog highlights the recent enhancements made to the Multi-Technology Simulation…

• 2 min read
ICADVM18.1 , ADE Explorer , Virtuoso Analog Design Environment , Spectre , Virtuoso Video Diary , Multi-Technology Simulation , Custom IC , IC6.1.8 , ADE Assembler , MTS

Breakfast Bytes

GLOBALFOUNDRIES Technology Conference 2019

This week was the GLOBALFOUNDRIES Technology Conference, GTC 2019, in Santa Clara…

• 5 min read
GTC , GlobalFoundries , FD-SOI

Breakfast Bytes

HOT CHIPS: The AWS Nitro Project

In 2016, Amazon acquired the Israeli company Annapurna Labs. Since they were in stealth…

• 6 min read
ec2 , nitro , cloud , annapurna , aws , Amazon

Whiteboard Wednesdays

Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA…

In this week's Whiteboard Wednesdays video, Tom Hackett continues his introduction…

• less than a min read
Whiteboard Wednesdays , FEM , Electromagnetic analysis , finite element analysis , Clarity 3D Solver , FEA

System, PCB, & Package Design 

IC Packagers: Wrap Your Hands Around a Coil

Coils are a design element that, if not exceedingly common, are showing up in more…

• 2 min read
SiP Layout

Breakfast Bytes

The 2019 Kaufman Award Goes to Mary Jane Irwin

This year's Kaufman Award recipient is Dr. Mary Jane (Janie) Irwin of Pennsylvania…

• 3 min read
Kaufman Award

Breakfast Bytes

TSMC OIP: Process Status

Last week was TSMC's Open Innovation Platform Innovation Forum (aka OIP). Dave Keller…

• 7 min read
OIP , TSMC

Breakfast Bytes

Sunday Brunch Video for 29th September 2019

https://youtu.be/zU_y5sQBlGA Made at TSMC OIP Symposium (camera Tom Hackett) Monday…

• less than a min read
sunday brunch

System, PCB, & Package Design 

BoardSurfers: PCB Electronics - Three Routing Challenges and Their Solutions

Routing is the core of a PCB. And, it's not an easy task. There are many challenges…

• 4 min read
PCB Layout and routing , PCB Editor

Analog/Custom Design

Virtuosity: Automated Device Placement and Routing—WSP-Based Tree Style Device R…

This blog provides an overview of the last step of the Virtuoso Automated Device…

• 4 min read
automatic routing , Pin to Trunk , ICADVM18.1 , Virtuoso Space-based Router , EXL , Automated Device-Level Placement and Routing , Automatic Placement , Virtuoso Placer , Layout EXL , Auto P&R , Virtuoso Placement , Placement , tree router , Custom IC Design

PCB、IC封装：设计与仿真分析

Ken的博客系列之八 | 千兆位串行链路接口的SI方法

作者：Ken Willis 上一篇：反向信道训练 自动合规性检查 有了详细的布局后互连以及IBIS-AMI模型的正确执行，您可以关注特定的、感兴趣的接口（本例中为PCI…

• less than a min read
SI , Chinese blog , ddr5 , 仿真分析 , DDR4 , IBIS-AMI , 中文 , SerDes , Sigrity , SystemSI , 信号完整性 , SI分析与建模

Breakfast Bytes

Building Neural Networks with High-Level Synthesis

Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus…

• 4 min read
deep learning , TensorFlow , Stratus , high level synthesis , HLS
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