Explore the Cadence Forums to find and exchange in-depth technical information.

Featured

Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Breakfast Bytes

RISC-V Cores: SweRV and ET-Maxion

December was the first RISC-V summit at the Santa Clara Convention Center. I covered…

• 6 min read
Western Digital , risc-v , esperanto , maxion , swerv

Digital Design

Glitch Noise Analysis and Fixing with Tempus

Every design engineer knows something about glitch but for many the details are a…

• 5 min read
SI , Tempus , STA , delay , noise , glitch , Signal Integrity , crosstalk , signoff , silicon signoff , Sign off , timing

Breakfast Bytes

IEDM: The World After Copper

I remember Gary Patton, the CTO of GLOBALFOUNDRIES, telling me once that research…

• 9 min read
interconnect , cobalt , copper , 3nm , contact , imec , amat , 5nm , IEDM , rubidium

Breakfast Bytes

150th Anniversary of the Periodic Table of the Elements

Happy New Year, and welcome to another year of Breakfast Bytes. This year is the…

• 5 min read
mendeleev , periodic table

Breakfast Bytes

Sunday Brunch Video for 1st January 2019

https://youtu.be/my0o9-PD-a8 Made at the Cadence EBC (camera Sean) Monday: CES Preview…

• less than a min read
The Economist , CES , flying , puzzle , hotels

Verification

Renesas Brings Their Legacy Testbench Up to Speed Using the Cadence Verification…

Recently, Renesas Electronics Corporation faced a challenge. They were developing…

• 1 min read
Specman , Functional Verification , Renesas , e , success

Breakfast Bytes

Silent Night

Happy Christmas from Breakfast Bytes. It's Christmas Eve 2018, and 200 years ago…

• 2 min read
silent night , anniversary , off topic , Christmas

Digital Design

Patterns, a Unified Language between Design and Manufacturing

There will be no design without manufacturing and manufacturing is mainly about patterns…

• 3 min read
pattern analysis , machine learning , yield , design for manufacturing , DFM

PCB、IC封装：设计与仿真分析

DDR5的时代已经到来

本文翻译自Cadence “Breakfast Bytes” 专栏作者Paul McLellan文章" DDR5 Is on Our Doorstep "。 space…

• less than a min read
Chinese blog , ddr5 , DDR4 , Micron , TSMC , DRAM , 中文

The India Circuit

7 Trends We Saw In 2018

I did at 2017 retrospective last year and looking back at 2018 there was a lot that…

• 3 min read
2019 , 2018 in review

Breakfast Bytes

Off Topic: Are You Smarter Than Google?

It's the day before Cadence is shut down for the holidays. Breakfast Bytes will resume…

• 7 min read
off topic , monty hall problem , are you smarter than google

Analog/Custom Design

Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download…

• 2 min read
Virtuoso ICADV12.3 , Analog Design Environment , ICADV12.3 , Routing , IC 6.1 , Mixed-Signal , Virtuoso , Schematic Editor , IC6.1.7 , Virtuoso IC6.1.7 , Virtuoso Layout Suite , ADE Assembler

Analog/Custom Design

Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing…

• 7 min read
spectre aps , Spectre EMIR , Virtuoso ADE , Spectre , EMIR , Voltus-Fi XL

Verification

Verification Reflections on 2018

In my predictions for 2018 I had identified five key trends driving verification…

• 5 min read
security , functional safety , verification

Breakfast Bytes

Top 10 Hotel Pet Peeves

When it comes to hotels, I have simple tastes. As long as the bed is comfortable…

• 10 min read
hotel , travel

System, PCB, & Package Design 

10 Things You Might Have Missed in 2018

We’re sure it’s been a busy year for you. So busy that you might have missed the…

• 2 min read
PCB , Cadence Design Systems , Symphony , Power Integrity , PCB design , Sigrity , DFM , Allegro

定制IC芯片设计

Virtuoso: 新序曲-针对团队设计的新方法—Concurrent Layout工具

任何任务，被划分为不同的小任务，并分配给不同的人，这样是不是能加速完成该工作？ 如果我们告诉您新发布的ICADVM18.1 中Layout XL的新特征- Concurrent…

• less than a min read
Chinese blog , Chip finishing , Virtuoso Next , Virtuoso Overture , ICADVM18.1 , Virtuoso New Design Platform , Virtuoso Advanced Release , Layout , Custom IC Design , Virtuoso Layout Suite , VLS XL , Virtuoso Layout Suite XL

Breakfast Bytes

The Breakfast Bytes Guide to Flying

I fly a fair bit, a little over 100,000 miles a year in the last few years. There…

• 9 min read
flying

Life at Cadence

What Makes Cadence a Great Place to Work?

Cadence was recently named number 15 on the 2018 list of the World’s Best Multinational…

FormerMember • 2 min read
World's Best , Insights on Culture , Culture , Work that matters , GPTW , great place to work
CDNS - Fix Layout Hompage